Self-Aligned Trench MOSFET Contacts Beyond Lithography Limits
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Solution Overview
Problem
Current trench MOSFET manufacturing is limited by lithographic capabilities, which restrict device pitch to around 200-300 nm, hindering further reduction in channel resistance (RON) and device density.
Innovation Solution
The use of sacrificial spacers during the fabrication process allows for self-aligned contact formation, effectively reducing device pitch to half of the lithographic limit without altering lithography processes, by forming and removing spacers to align contacts with gate trenches, enabling smaller Si mesa widths and higher body/source ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If lithographic processes are used to locate devices closer together, then device pitch is reduced, but device pitch cannot go below 200-300 nm due to lithographic limits
Solution Approach 1:
The fabrication process is divided into multiple stages: first forming gate trenches at lithographic limits, then adding sacrificial spacers to define contact trenches. This segmentation allows the final device pitch to be half the lithographic limit by combining two separate patterning operations rather than attempting to pattern all features in a single lithographic step.
Solution Approach 2:
Gate trenches are formed first using conventional lithography, then sacrificial spacers are deposited and patterned on top. This preliminary formation of gate structures enables subsequent self-aligned contact trench formation at smaller dimensions without requiring advanced lithography for the final contact alignment.
2Reliability
If device pitch is reduced to lower channel resistance, then current handling capacity increases, but device pitch is limited by lithographic minimums
Solution Approach 1:
The patent transitions from planar patterning to three-dimensional self-aligned patterning by depositing vertical sacrificial spacers on top of patterned gate trenches. This dimensional transition enables contact trench formation at half the lithographic pitch by utilizing the vertical spacer structure rather than relying solely on lateral lithographic resolution.
3Length of moving object
If self-aligned contact formation is used, then device pitch is reduced to half lithographic limit, but fabrication process complexity increases
Solution Approach 1:
The sacrificial spacers automatically define the contact trench positions based on the gate trench locations, creating self-aligned contacts without requiring additional lithographic alignment steps. The spacer structures serve their own purpose as alignment references, eliminating the need for complex multi-step lithographic alignment procedures.
Data Source
AI summary
Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.