Self-Aligned MOSFET Trenches Using Sacrificial Spacer Pillars
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Solution Overview
Problem
Existing semiconductor manufacturing processes are limited by lithographic capabilities, preventing further reduction of device pitch beyond 200nm or 300nm, which hinders the reduction of channel resistance and current capacity in trench MOSFET devices.
Innovation Solution
The use of sacrificial spacers on either side of hard mask pillars during fabrication, allowing for self-aligned contact formation without altering lithography processes, resulting in a device pitch half the lithographic limit and improved body/source ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If lithographic processes are used to locate devices, then device pitch can be reduced to about 200nm or 300nm, but device pitch cannot be reduced further beyond this limit
Solution Approach 1:
The patent divides the device formation process into multiple stages: first forming mandrels at a relaxed pitch, then adding sacrificial spacers to create additional features at half the original pitch. This segmentation allows the final device pitch to be half the lithographic limit without requiring advanced lithography
Solution Approach 2:
Sacrificial spacers are introduced as intermediary structures during fabrication. These spacers are formed on mandrels, then the mandrels are removed, leaving the spacers as the final device features. The spacers act as a mediator that enables sub-lithographic pitch formation through self-aligned processes
2Reliability
If device pitch is reduced to lower channel resistance, then current capacity increases, but lithographic capabilities are exceeded
Solution Approach 1:
Mandrels are formed in advance at a larger pitch that is within lithographic capabilities. The sacrificial spacers are then added to these pre-formed mandrels, and the mandrels are removed. This preliminary action allows the final small-pitch features to be created without directly lithographing them, reducing lithographic complexity while achieving the desired current capacity
3Length of moving object
If additional techniques are used to reduce device pitch beyond lithographic limits, then device pitch decreases, but manufacturing process complexity increases
Solution Approach 1:
The sacrificial spacers are self-aligned to the mandrels through conformal deposition, eliminating the need for additional lithographic alignment steps. The spacers automatically position themselves at the correct locations and orientations, making the sub-lithographic pitch formation process simpler than conventional multi-step lithographic approaches would require
Data Source
AI summary
Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.