Self-Aligned MRAM Array Patterning via Dielectric Spacers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current magnetic memory devices, particularly cross-point MRAM arrays, face challenges in efficiently manufacturing and optimizing the structure of spin-transfer torque (STT) and spin-orbit-torque (SOT) MRAM cells, which affect data storage and retrieval due to complexities in layer formation and interconnectivity.
Innovation Solution
The development of a memory array structure comprising laterally extending electrically conductive lines, selector-containing pillar structures, and magnetic tunnel junction (MTJ) pillar structures, with specific patterning and dielectric spacer formations to create a precise and efficient array configuration for MRAM cells, enabling improved data storage and retrieval processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic patterning is used to form magnetic memory structures, then manufacturing process is simpler, but manufacturing precision and feature size control deteriorate
Solution Approach 1:
The patent applies preliminary action by forming mandrel structures and sacrificial layers before final patterning. The self-aligned patterning process uses preliminary deposition of dielectric materials and conductive layers that automatically align subsequent features, achieving high precision without complex lithographic steps. The mandrel-based approach pre-establishes geometric constraints that guide final feature formation.
Solution Approach 2:
The patent introduces intermediary structures such as dielectric spacers and sacrificial mandrels that mediate between the lithographic pattern and final magnetic memory features. These intermediary elements enable precise feature definition through self-aligned processes, where the spacer width (controlled by conformal deposition) directly determines the final interconnect dimension, bypassing lithographic resolution limits.
2Quantity of substance
If feature size is reduced to increase storage density, then storage capacity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from two-dimensional lithographic patterning to three-dimensional self-aligned patterning using vertical dielectric spacers. The critical dimension control moves from lateral lithographic resolution to vertical film thickness control through atomic layer deposition or chemical vapor deposition, enabling precise sub-10nm feature sizes that increase storage density while maintaining manufacturability.
Solution Approach 2:
The patent changes the controlling parameter for feature size from lithographic wavelength to thin film deposition thickness. By using conformal dielectric spacer deposition where the spacer width equals twice the film thickness, the process achieves atomic-level precision (±1nm or better) compared to lithographic limitations, enabling continued scaling for higher storage density.
3Reliability
If complex interconnect structures are formed to improve cell functionality, then device performance improves, but ease of manufacture deteriorates
Solution Approach 1:
The patent merges multiple patterning steps into a single self-aligned process. The dielectric spacer formation simultaneously defines word line and bit line positions, eliminates the need for separate alignment steps, and automatically ensures orthogonal interconnect geometry. This consolidation maintains complex three-dimensional interconnect functionality while dramatically simplifying the manufacturing sequence.
Solution Approach 2:
The self-aligned patterning process is self-service in that the conformal dielectric spacer automatically positions and sizes the interconnect features without external alignment guidance. The spacer width is self-determined by the deposition thickness, and the pattern transfer to underlying layers occurs automatically through the spacer's geometric constraint, eliminating the need for complex lithographic alignment procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the efficiency and reliability of data storage and retrieval in MRAM cells by optimizing the structural layout and interconnectivity of MRAM cells, addressing the manufacturing challenges and improving the overall performance of magnetic memory devices.
Implementation Method 1
Spin-transfer torque (STT) refers to an effect in which the orientation of a magnetic layer in a magnetic tunnel junction or spin valve is modified by a spin-polarized current
Implementation Method 2
A spin polarized current is one in which electrons have a net non-zero spin due to a preferential spin orientation distribution
Implementation Method 3
Spin-orbit-torque (SOT) MRAM devices use switching of magnetization direction of a free magnetic layer by injection of an in-plane current in an adjacent conductive layer, which is referred to as a spin-orbit-torque (SOT) layer
Implementation Method 4
A resistance differential of a magnetic tunnel junction between different magnetization states of the free layer can be employed to store data within the magnetoresistive random access memory (MRAM) cell
Data Source
AI summary
A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.