Self-Aligned Multi-Height Interconnects for Resistance-Capacitance Tuning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuit (IC) metallization features scale down with increasing interconnect density, parasitic electrical resistance and line-to-line capacitance lead to higher power consumption and degraded performance, necessitating advanced interconnect architectures that can effectively manage multi-height vias and lines to tune resistance and capacitance independently.
Innovation Solution
The implementation of multi-height vias and lines within a single interconnect level, where vias and lines of complementary heights are self-aligned and formed from a conductive material stack, allowing for independent tuning of resistance and capacitance, and are fabricated using subtractive patterning techniques to reduce parasitic resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If metallization features are scaled down to increase interconnect density, then interconnect density is improved, but parasitic electrical resistance increases leading to higher power consumption
Solution Approach 1:
The patent divides the interconnect structure into multi-height lines and multi-height vias within the same interconnect level. This segmentation allows different functional blocks to use lines and vias of optimized heights, independently tuning resistance and capacitance to reduce power consumption while maintaining high density.
Solution Approach 2:
The patent applies local quality by allowing different regions of the interconnect level to have different line and via heights. Shorter lines/vias can be used in regions where low capacitance is critical, while taller lines/vias can be used where low resistance is more important, optimizing overall power efficiency.
2Quantity of substance
If metallization features are scaled down to increase interconnect density, then interconnect density is improved, but parasitic electrical resistance increases degrading performance
Solution Approach 1:
By segmenting the interconnect level into multi-height lines and vias, the patent enables performance optimization for different signal types and functional blocks. Critical performance paths can use taller structures with lower resistance, while non-critical paths use shorter structures, maintaining overall high density.
3Loss of energy
If line-to-line capacitance is reduced to improve power consumption, then power consumption is improved, but interconnect density may be limited
Solution Approach 1:
The patent introduces vertical dimensionality variation within the same interconnect level by using multi-height lines and vias. This allows capacitance optimization through height reduction in specific areas without compromising horizontal density, as the density benefit comes from the integrated use of both short and tall structures across the level.
4Loss of energy
If multi-height lines and vias are integrated to independently tune resistance and capacitance, then power efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges the formation of lines and vias into a unified subtractive patterning process. By using the same etch process to define both lines and vias from a common conductive material stack, the patent reduces fabrication complexity despite the multi-height structure, making the power-efficient design manufacturable.
5Loss of energy
If subtractive patterning is used to form multi-height lines and vias, then parasitic resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple patterning operations into a single subtractive patterning step. By defining both lines and vias simultaneously through one etch process using a common conductive material stack, the patent achieves low parasitic resistance without proportionally increasing manufacturing complexity.
Solution Approach 2:
The subtractive patterning process is self-aligning, where the same etch process that defines lines automatically defines vias. This self-service characteristic reduces the need for additional alignment steps and complex manufacturing procedures, offsetting the complexity of forming multi-height structures.
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
Integrated circuitry comprising an interconnect level with multi-height lines contacted by complementary multi-height vias. In some examples, a first line of a taller height is contacted by a first via of a shorter height while a second line of a shorter height is contacted by a second via of a taller height. The first and second vias and first and second lines may be subtractively defined concurrently from a same stack of conductive material layers such that the first via comprises a first conductive material layer, and the first line comprises second and third conductive material layers while the second via comprises the first and second conductive material layers and the second line comprises the third conductive material layer.