Self-Aligned Nanopore Transistor Layout for Precise Biosensing
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Solution Overview
Problem
Current nanopore transistor technologies face challenges in accurately forming and positioning nanopores on fin structures for biosensing applications, particularly in achieving precise alignment and small nanopore sizes required for DNA or RNA sequencing, which is costly and complex with existing lithography methods.
Innovation Solution
A method for forming nanopore transistors that involves creating a fin structure with a bottom semiconductor layer and a top layer, patterning the top layer to form a pillar, embedding it in a filler material, and etching a nanopore through the aperture, while aligning the nanopore self-aligned laterally and allowing for reduced fin width and low-cost mass production, enabling precise positioning and adaptable nanopore sizes without additional lithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If 193 nm lithography is used to define nanopore position, then alignment precision can be achieved, but manufacturing cost increases and resolution is insufficient for narrow nanowires
Solution Approach 1:
The nanopore position is predetermined by the fin structure geometry itself. The fin is formed with specific dimensions and positioning that inherently define where the nanopore should be located, eliminating the need for separate lithography alignment steps. This preliminary structuring of the fin allows subsequent processing to automatically achieve precise nanopore placement without additional costly lithography operations.
Solution Approach 2:
The fin structure serves multiple functions: it provides mechanical support, defines the nanopore position through its geometry, and guides the etching process. The fin's own structural characteristics (width, length, position) automatically determine the nanopore location, making the system self-aligning and eliminating dependency on external lithography alignment processes.
2Manufacturing precision
If multiple lithography masks are used to position nanopore, source, and drain, then alignment accuracy improves, but device complexity and manufacturing steps increase
Solution Approach 1:
The fin structure combines multiple functions into a single element: it provides mechanical support, defines the nanopore position through its geometry, and serves as the substrate for source and drain formation. By merging these functions into one integrated structure rather than treating them as separate elements requiring separate alignment, the number of lithography masks and processing steps is significantly reduced.
Solution Approach 2:
The fin structure acts as a universal element that simultaneously performs structural support, positioning reference, and device fabrication guide functions. This multi-functionality allows a single fin structure to determine the positions of multiple critical elements (nanopore, source, drain) without requiring separate positioning mechanisms for each, thereby simplifying the overall device complexity and manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of nanopore transistors with high precision and alignment, reducing the drive current and enabling efficient biosensing, particularly for DNA sequencing, while minimizing production costs and complexity.
Implementation Method 1
The voltage potential applied across the drain and source regions creates a gradient that causes the biopolymer to move through the opening
Implementation Method 2
the sequence of bases may induce charges, which can form a conducting channel in the semiconductor channel region between the drain and source regions, resulting in a current variation that can be detected
Data Source
AI summary
A method for forming a nanopore transistor and a nanopore transistor is provided. The method includes: (a) forming an aperture in a filler material by: (i) providing a fin comprising a semiconductor layer and a top layer; (ii) patterning the top layer to form a pillar; (iii) embedding the pillar in a filler material; (iv) removing the pillar, leaving an aperture; (v) lining the aperture with a spacer material; (b) forming a nanopore by etching through the aperture; (b) lining the nanopore with a dielectric, (c) forming a source and a drain by either: between steps a.ii and a.iii, doping the bottom semiconductor layer by using the pillar as a mask, or after step c, filling the aperture with a sealing material, thereby forming a post; removing the filler material; doping the bottom semiconductor layer by using the post as a mask; and removing the sealing material.


