Self-Aligned 3D Nanosheet Layout for Dense Transistor Stacking
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Solution Overview
Problem
Existing semiconductor device fabrication processes face challenges in scaling beyond single digit nanometer nodes, particularly in transitioning from two-dimensional to three-dimensional circuits, where transistor stacking is desired but difficult to achieve efficiently.
Innovation Solution
A method of microfabrication involving epitaxial growth to form a stack of semiconductor layers with alternating channel structures and sacrificial gate layers, followed by selective etching and replacement with gate structures, enabling self-aligned nanosheet formation with reduced masking layers and increased transistor density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2D fabrication processes are used to scale transistors, then transistor density per unit area increases, but manufacturing complexity and difficulty increase significantly at single digit nanometer nodes
Solution Approach 1:
The patent transitions from 2D planar transistors to 3D vertically-stacked nanosheet transistors. Multiple channel structures are stacked vertically above each other, enabling higher transistor density without proportionally increasing fabrication complexity. The vertical stacking allows more transistors to be packed into the same footprint area.
Solution Approach 2:
The transistor channel is segmented into multiple thin nanosheet layers stacked vertically. Each nanosheet acts as an independent channel structure, allowing the channel to be divided into discrete functional units that can be controlled individually while sharing common source/drain regions.
2Quantity of substance
If 3D transistor stacking is implemented, then transistor density increases, but process steps and manufacturing difficulty increase
Solution Approach 1:
Source/drain regions are formed prior to the formation of gate structures. This preliminary action allows the source/drain regions to be self-aligned with the channel structures, eliminating the need for additional alignment steps and dummy gates that would otherwise be required in conventional approaches.
Solution Approach 2:
The method uses self-aligned processes where previously formed structures serve as alignment references for subsequent steps. The source/drain regions formed in earlier steps automatically provide alignment references for gate structure formation, eliminating the need for separate alignment procedures and reducing process complexity.
3Ease of manufacture
If conventional gate formation methods are used, then gate structures can be formed, but additional process steps including dummy gates are required
Solution Approach 1:
The method eliminates the need for dummy gates by forming source/drain regions before gate structures. This extraction of the dummy gate requirement simplifies the overall process by removing unnecessary structures and steps that would otherwise be needed to achieve proper alignment and device functionality.
4Reliability
If selective etching and protective structures are used for channel release, then transistor performance improves, but process steps increase
Solution Approach 1:
Protective structures are applied selectively to specific regions during the etching process. Different portions of the structure receive different levels of protection, allowing precise control over which channels are released and which remain protected. This local differentiation enables optimized transistor performance while managing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the production of high-density, cost-effective 3D semiconductor circuits with improved transistor performance by maximizing channel release and source/drain formation, eliminating the need for dummy gates and reducing process steps.
Implementation Method 1
forming an initial stack of semiconductor layers by epitaxial growth over a substrate
Implementation Method 2
First portions of the sidewall structure are removed to uncover first sides of the initial stack. Second portions of the sidewall structure are removed to uncover second sides of the initial stack.
Data Source
AI summary
A method of microfabrication includes forming an initial stack of semiconductor layers by epitaxial growth over a substrate. The initial stack of semiconductor layers is surrounded by a sidewall structure. The initial stack of semiconductor layers includes channel structures and sacrificial gate layers stacked alternatingly in a vertical direction substantially perpendicular to a working surface of the substrate. The channel structures include a first channel structure and a second channel structure positioned above the first channel structure. First portions of the sidewall structure are removed to uncover first sides of the initial stack. Source/drain (S/D) regions are formed on uncovered side surfaces of the channel structures from the first sides of the initial stack. Second portions of the sidewall structure are removed to uncover second sides of the initial stack. The sacrificial gate layers are replaced with gate structures from the second sides of the initial stack.