Self-Aligned ONO Film Formation for SONOS Flash Memory
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Solution Overview
Problem
Existing SONOS type flash memory devices face issues with asymmetrical ONO film lengths due to misaligned photoresist patterns, leading to non-uniform threshold voltages and erase rates across memory cells, resulting in high power consumption, reduced read speed, and compromised data retention.
Innovation Solution
A self-aligned electron trap film is formed with symmetrical dielectric film lengths by using a method involving multiple gate electrodes and conductive films, where the first and second gate electrodes are formed on dielectric films with heights higher than the third gate electrode, and a fourth gate electrode is electrically connected to them, allowing for a self-aligned dielectric film formation without additional mask processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a photoresist pattern is used as a mask to form the gate, then the gate structure can be defined, but misalignment occurs causing asymmetrical ONO film lengths
Solution Approach 1:
The gate electrode structure itself serves as the alignment reference for forming the ONO film. The self-aligned process uses the gate electrode's physical presence to define the ONO film boundaries, eliminating the need for separate photoresist masks and their associated alignment problems.
Solution Approach 2:
The gate electrode is formed first as a preliminary structure that will subsequently serve as the alignment reference for the ONO film formation. This preliminary gate structure enables precise positioning of the ONO film without requiring additional masking steps.
2Adaptability or versatility
If the ONO film length varies across cells, then the gate can accommodate different regions, but threshold voltage uniformity deteriorates
Solution Approach 1:
The gate electrode automatically defines the ONO film length through self-alignment, ensuring uniform threshold voltage across all cells while still covering the necessary gate region. The self-aligned process inherently provides consistent dimensions without requiring additional control measures.
3Reliability
If electrons are trapped at the silicon nitride film, then flash memory function is achieved, but erase operation efficiency decreases
Solution Approach 1:
The patent modifies the dielectric film structure by introducing a self-aligned ONO film with controlled thickness and composition. This parameter change optimizes the balance between electron trapping capability for data retention and erase efficiency by preventing horizontal electron movement while maintaining vertical trapping.
Data Source
AI summary
A semiconductor device and a method of manufacturing the same, wherein first and second gate electrodes are formed to have a spacer shape. The length of an underlying dielectric film can be automatically controlled. A gate oxide film and a third gate electrode are formed between the first and second gate electrodes. Voids are not generated when burying the third conductive film. A thickness and width of the gate oxide film can be freely controlled.