Self-Aligned Passivation for FinFET Interfacial State Reduction

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Solution Overview

Problem

The formation of FinFETs results in dangling bonds on semiconductor fin surfaces, leading to increased Density of Interfacial States (Dit) and degradation of carrier mobility and drive currents due to the etching and cleaning processes involved in their formation.

Innovation Solution

A method involving self-aligned passivation steps using specific passivation species to eliminate dangling bonds on different surface planes of semiconductor fins, including sulfur, selenium, antimony, arsenic, and chlorine, which selectively form passivation bonds on preferred surface planes, reducing Dit and enhancing FinFET performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If etching and cleaning processes are used to form semiconductor fins, then FinFET structure is formed, but dangling bonds are generated on fin surfaces leading to increased Dit and degraded carrier mobility

Engineering Contradiction:
ImproveFinFET structure formationVSAvoidCarrier mobility
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A passivation layer is deposited on the semiconductor fin surfaces before subsequent processing steps. This preliminary passivation prevents dangling bonds from forming during etching and cleaning operations, thereby maintaining high carrier mobility while enabling FinFET structure formation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a passivation layer as an intermediary between the fin formation processes and the final device operation. This intermediate layer protects the fin surfaces from damage during manufacturing while allowing the FinFET structure to be formed, thus resolving the contradiction between structure formation and carrier mobility preservation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If multiple passivation species are used on different surface planes, then Dit is reduced and carrier mobility is enhanced, but process complexity increases

Engineering Contradiction:
ImproveCarrier mobilityVSAvoidPassivation process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different passivation species to different crystallographic planes of the semiconductor fin surfaces. Specifically, sulfur is applied to (100) planes while selenium is applied to (110) planes. This localized differentiation reduces Dit more effectively than uniform passivation, accepting increased process complexity as a necessary trade-off for achieving superior electrical performance.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces the Density of Interfacial States and improves the performance of FinFETs by eliminating dangling bonds, thereby enhancing carrier mobility and drive currents.

Implementation Method 1

performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species

Methodology Applied
Scientific EffectChemical bonding: Chemical Bonding

Data Source

PatentUS10943995B2Self-aligned passivation of active regions
Publication Date: 2021.03.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10943995B2 patent drawing
  • US10943995B2 patent drawing
  • US10943995B2 patent drawing

AI summary

A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).