Self-Aligned Multiple Patterning for Edge Placement Accuracy
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Solution Overview
Problem
As semiconductor devices approach technological limits, achieving accurate feature-to-feature positioning during multiple patterning processes becomes increasingly difficult, leading to edge placement errors and defects such as footing structures, corner rounding, and pitch dimension inaccuracies, which can result in device failure.
Innovation Solution
The method employs self-aligned litho-etch-litho-etch (SALELE) with spacer patterning, involving multiple lithography-and-etch processes and gap-filling steps to form nanostructures with increased edge placement error margins, using a spacer layer to enhance feature density and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional optical lithography is used to pattern features, then the manufacturing process is simple, but the manufacturing precision deteriorates due to edge placement errors and inability to achieve accurate feature-to-feature positioning
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple discrete steps (first lithography-and-etch process, second lithography-and-etch process, spacer patterning, gap-filling processes). Each step creates intermediate structures that are combined to form the final high-precision pattern, allowing complex positioning requirements to be met through sequential simpler operations
Solution Approach 2:
The patent employs preliminary action through the formation of spacer layers on mandrel sidewalls before final pattern transfer. The spacers are formed in advance with controlled thickness and positioning, serving as self-aligned reference structures that define subsequent feature locations with high precision, eliminating the need for additional alignment steps
2Manufacturing precision
If multiple patterning processes are used to increase feature density, then the manufacturing precision improves, but the device complexity increases due to multiple lithography and etch steps
Solution Approach 1:
The patent implements self-service through self-aligned spacer formation where the spacer layer automatically positions itself on the mandrel sidewalls based on the mandrel's geometry. This self-alignment mechanism eliminates the need for separate alignment operations between patterning steps, reducing process complexity while maintaining high feature density control
Solution Approach 2:
The patent applies the nested doll principle by forming structures within structures - spacers are formed on mandrel sidewalls, then gap-filling layers are deposited in the spaces between spacers, creating nested hierarchical structures. This allows multiple features to be created through nested deposition and etching operations rather than separate lithography steps
3Productivity
If feature dimensions are reduced to push technology limits, then the productivity improves by enabling smaller devices, but the manufacturing precision deteriorates due to increased edge placement errors
Solution Approach 1:
The patent uses the spacer layer as an intermediary structure between the lithographically-defined mandrel and the final target pattern. The spacer's thickness, controlled by atomic layer deposition with precise thickness control, acts as the critical dimension definition mechanism, decoupling the feature size from direct lithographic resolution limits and enabling accurate sub-10nm features
Solution Approach 2:
The patent replaces the mechanical/optical alignment system with a chemical vapor deposition-based spacer formation process. Instead of relying on optical lithography resolution and alignment mechanics, the critical dimensions are defined by conformal film deposition thickness, which can be controlled at the nanometer and sub-nanometer scale through vapor-phase chemical reactions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of nanostructures with higher feature density and increased error margins, effectively reducing defects and improving the precision of semiconductor device manufacturing beyond conventional optical lithography limits.
Implementation Method 1
forming a spacer layer on sidewalls of the patterned mandrel layer
Implementation Method 2
forming a spacer layer on sidewalls of the patterned mandrel layer
Implementation Method 3
forming a gap-filling layer in openings of the spacer layer
Data Source
AI summary
A method for forming a nanostructure on a substrate includes performing a first lithography-and-etch process, including patterning a mandrel layer disposed on a first dielectric layer, performing a spacer patterning process, including forming a spacer layer on sidewalls of the patterned mandrel layer, performing a first gap-filling process, including forming a gap-filling layer in openings of the spacer layer on the first dielectric layer and over the patterned mandrel layer, performing a second lithography-and-etch process, including patterning the gap-filling layer and further patterning the patterned mandrel layer, performing a second gap-filling process, including further forming the gap-filling layer in openings of the twice patterned mandrel layer, and performing a spacer removing process, including removing the patterned spacer layer and the twice patterned mandrel layer.