Self-aligned Phase Change Memory Cell with Fin Bottom Electrode
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Solution Overview
Problem
Current non-volatile memory technologies face challenges such as high voltage requirements, high resistance values, and misalignment issues in fabricating phase change memory cells, which limit their scalability and performance, especially in the sub-10 nm range.
Innovation Solution
A self-aligned embedded phase change memory cell is developed, where the phase change material layer is aligned with the conductive bitline, reducing misalignment and allowing for the formation of self-aligned PCM memory cells with a rectangular bottom electrode fin, enabling efficient fabrication and integration in advanced semiconductor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for phase change memory cells, then manufacturing simplicity is maintained, but misalignment between phase change material layer and conductive bitline occurs, reducing manufacturing precision
Solution Approach 1:
The conductive bitline is formed first as a preliminary structure, and then the phase change material layer is deposited to be self-aligned with the bitline. This preliminary action of forming the bitline before the phase change material ensures precise alignment without requiring additional alignment steps during subsequent fabrication processes.
Solution Approach 2:
The phase change material layer automatically aligns itself with the conductive bitline through the self-aligned fabrication process. The material deposition process inherently follows the bitline geometry, allowing the structure to self-align without external intervention or complex alignment machinery.
2Reliability
If existing non-volatile memory technologies are used, then memory capacity is achieved, but high voltage requirements and high resistance values limit scalability and performance
Solution Approach 1:
The invention changes the electrical parameters of the memory cell by using a specifically engineered phase change material composition and structure. This results in lower resistance values and reduced operating voltage requirements compared to conventional non-volatile memory technologies, enabling better integration with standard CMOS logic processes.
Solution Approach 2:
The phase change material layer uses a composite composition containing germanium, antimony, and tellurium in specific proportions. This composite material provides optimized electrical properties including lower resistance and reduced voltage requirements while maintaining non-volatile memory functionality and reliability.
3Productivity
If feature size is reduced to increase device density, then capacity increases, but variability in fabrication processes limits extension into sub-10 nm range
Solution Approach 1:
The invention transitions from planar two-dimensional patterning to a three-dimensional self-aligned approach. By forming the phase change material layer that conforms to the vertical sidewalls of the conductive bitline, the process adds a vertical dimension to the structure, enabling precise alignment even as horizontal feature sizes shrink to sub-10 nm ranges.
Solution Approach 2:
The memory cell structure is segmented into distinct functional layers with the phase change material forming a specific geometric shape (e.g., cylindrical or rectangular prism) that is spatially separated and self-aligned with the conductive bitline. This segmentation allows each component to be optimized independently while maintaining precise relative positioning through the self-aligned fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the scalability and performance of phase change memory cells by reducing misalignment and enabling operation at lower voltages, compatible with CMOS logic processes, thus addressing the limitations of existing technologies.
Implementation Method 1
a memory element coupled between the bottom electrode and the conductive line, the memory element comprising a phase change material layer
Data Source
AI summary
An integrated circuit comprising a self-aligned embedded phase change memory cell is described. In an example, the integrated circuit includes a bottom electrode. A conductive line is above the bottom electrode along a first direction above a substrate. A memory element is coupled between the bottom electrode and the conductive line, the memory element comprising a phase change material layer that is self-aligned with the conductive line.