Self-Aligned Pillar Semiconductor Structure for Memory Integration
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Solution Overview
Problem
Existing semiconductor device manufacturing processes face challenges such as misalignment between selection gates and pillar-shaped semiconductor layers, decreased charge mobility due to crystal grain boundaries, and difficulties in forming diffusion layers in thin silicon pillars, which affect the integration density and performance of memory devices.
Innovation Solution
A semiconductor device structure and manufacturing method that forms fin-shaped semiconductor layers with pillar-shaped layers on a substrate, using a metal-gate-last process, self-alignment techniques with two masks, and omitting the diffusion layer formation in the upper portion of the pillar-shaped semiconductor layer, allowing for reduced misalignment and increased integration density while maintaining single-crystal quality and improving read rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photo-etching is used to isolate the selection gate transistor layer, then the selection gate can be formed, but misalignment between the selection gate and pillar-shaped amorphous silicon layer occurs and extra spaces for mask alignment are required
Solution Approach 1:
The patent applies preliminary action by forming the pillar-shaped semiconductor layer first, then using it as a reference for subsequent self-aligned formation of the selection gate. The etch holes are formed through the insulating film and control gate to expose the pillar-shaped layer, ensuring precise alignment without requiring additional mask alignment steps.
Solution Approach 2:
The patent employs self-service through self-aligned etching where the pillar-shaped semiconductor layer itself serves as the alignment reference for forming the selection gate. The etch process automatically aligns the selection gate with the pillar-shaped layer by using the layer's physical structure as the guide, eliminating the need for external mask alignment.
2Ease of manufacture
If amorphous silicon or polycrystalline silicon is used to form the pillar-shaped silicon layer, then the layer can be deposited, but crystal grain boundaries decrease the charge mobility and read rate
Solution Approach 1:
The patent applies parameter changes by transitioning from amorphous or polycrystalline silicon to single-crystal silicon for the pillar-shaped semiconductor layer. This material parameter change eliminates crystal grain boundaries, thereby improving charge mobility and read rate while maintaining the feasibility of layer formation through standard semiconductor fabrication processes.
3Quantity of substance
If the silicon pillar becomes thinner to increase integration density, then more memory cells can be packed, but it becomes increasingly difficult to allow an impurity to exist in the silicon pillar
Solution Approach 1:
The patent applies parameter changes by using single-crystal silicon with controlled doping to achieve the desired impurity levels in thin silicon pillars. The single-crystal structure provides better control over impurity distribution and concentration, enabling precise threshold voltage adjustment even in thinner pillars where impurity control is critical.
4Ease of manufacture
If extra spaces for mask alignment are provided to cover the pillar-shaped amorphous silicon layer, then photo-etching can be performed, but the area needed for one pillar-shaped amorphous silicon layer is increased
Solution Approach 1:
The patent employs self-service through self-aligned etching where the pillar-shaped semiconductor layer serves as its own alignment reference. This eliminates the need for additional mask alignment spaces, as the etch process automatically positions the selection gate relative to the pillar-shaped layer through the physical structure itself, thereby reducing the area required per device.
Data Source
AI summary
A semiconductor device includes a fin-shaped semiconductor layer disposed on a semiconductor substrate, a first insulating film disposed around the fin-shaped semiconductor layer, a first pillar-shaped semiconductor layer disposed on the fin-shaped semiconductor layer, a first gate insulating film that is disposed around the first pillar-shaped semiconductor layer and includes a charge storing layer, a second gate insulating film disposed around the first pillar-shaped semiconductor layer and at a position higher than the first gate insulating film, a fifth gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer, and a first contact electrode surrounding the fifth gate insulating film.