Self-Aligned PIP Structure for Stable Split Gate Spacing
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Solution Overview
Problem
Conventional high voltage devices face challenges in minimizing size due to thick RESURF oxide layers, leading to prolonged gate-split gate distances and deformation of split gates, complicating manufacturing processes.
Innovation Solution
A polysilicon-insulator-polysilicon (PIP) structure is introduced, where polysilicon regions and insulation regions are formed through self-aligned processes, allowing precise control of gate-split gate distance and preventing deformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the RESURF oxide layer is increased to ensure proper insulation, then the gate-split gate distance is prolonged, but the device size increases and manufacturing precision deteriorates due to split gate tilt
Solution Approach 1:
The patent transitions from a conventional planar gate structure to a three-dimensional PIP structure where the split gate is positioned at a different vertical level (higher than the main gate) and connected via an insulating bridge. This dimensional change allows the gate-split gate distance to be effectively reduced in the horizontal plane while maintaining adequate insulation through the vertical separation provided by the insulating bridge, thus resolving the contradiction between insulation requirements and manufacturing precision.
2Reliability
If the thickness of the RESURF oxide layer is increased, then insulation is improved, but the distance between gate and split gate is prolonged, increasing device area
Solution Approach 1:
By elevating the split gate to a higher vertical level and connecting it to the main gate through an insulating bridge, the patent utilizes the vertical dimension to provide insulation. This allows the horizontal distance between gate and split gate to be minimized, thereby reducing the overall device area while maintaining adequate insulation performance through the vertical separation.
Solution Approach 2:
The insulating bridge structure effectively nests the split gate above the main gate structure, with the bridge extending downward to connect to the gate level. This nesting arrangement allows compact integration of both gates within a smaller horizontal footprint while maintaining the necessary insulation distance through the vertical extension of the bridge structure.
3Reliability
If multiple layers (spacer layer, self-aligned oxide layer, RESURF oxide layer) are stacked between gate and split gate, then insulation is ensured, but the split gate drifts and deforms, complicating manufacturing
Solution Approach 1:
The patent extracts and eliminates the complex multi-layer stacking structure (spacer layer, self-aligned oxide layer, RESURF oxide layer) from between the gate and split gate. Instead, it employs a simplified structure where the split gate is positioned above the main gate and connected via a single insulating bridge, removing the problematic intermediate layers that caused drift and deformation while maintaining insulation functionality.
Solution Approach 2:
By moving the split gate to a higher vertical dimension and connecting it through an insulating bridge, the patent eliminates the need for multiple horizontal insulation layers. This dimensional reorganization simplifies the structure to essentially one primary insulation layer (the bridge) rather than multiple stacked layers, thereby reducing manufacturing complexity and preventing gate deformation.
Data Source
AI summary
A polysilicon-insulator-polysilicon (PIP) structure includes: a first polysilicon region formed on a substrate; a first insulation region formed outside one side of the first polysilicon region and adjoined to the first polysilicon region in a horizontal direction; and a second polysilicon region formed outside one side of the first insulation region. The first polysilicon region, the first insulation region and the second polysilicon region are adjoined in sequence in the horizontal direction. The second polysilicon region is formed outside the first insulation region by a first self-aligned process step, and the first insulation region is formed outside the first polysilicon region by a second self-aligned process step.