Self-Aligned Polysilicon Resistor Between FET Gates
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Solution Overview
Problem
The formation of polysilicon resistors in integrated circuit structures requires additional mask steps, which are time-consuming and expensive, as they are not self-aligned with other structures and need to be formed in a different area with no gate dielectric layer, leading to inefficiencies in the manufacturing process.
Innovation Solution
A self-aligned polysilicon resistor is formed between gate structures in a field effect transistor area, using a polysilicon layer that is farther from the substrate than the gate structures, eliminating the need for additional mask steps by leveraging the same polysilicon layer used for a bipolar junction transistor, thus integrating the resistor formation with existing transistor fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If polysilicon resistors are formed separately from gate structures, then they can be positioned in desired areas, but additional mask steps are required which increase manufacturing time and cost
Solution Approach 1:
The patent merges the formation of polysilicon resistors with the formation of gate structures by using the same polysilicon layer and aligning both structures to a common reference plane (the lower surfaces of polysilicon bodies). This integration eliminates separate mask steps for resistor formation while maintaining precise positioning, directly resolving the contradiction between positioning accuracy and manufacturing efficiency
Solution Approach 2:
The patent creates a universal polysilicon layer that serves multiple functions: forming both gate structures and resistors. By establishing a common reference plane based on the lower surfaces of polysilicon bodies, the same layer and alignment process are used for both structure types, eliminating the need for separate masking operations and improving productivity without sacrificing positioning precision
2Productivity
If polysilicon resistors are formed at the same time as gate polysilicon bodies, then manufacturing steps are reduced, but they require different areas with no gate dielectric layer
Solution Approach 1:
The patent applies local quality by forming the polysilicon layer at different elevations in different areas: in FET areas, the polysilicon forms gate structures at a first elevation with gate dielectric, while in resistor areas, the polysilicon forms resistors at a second elevation without gate dielectric. This localized differentiation allows simultaneous formation of both structures using the same process while accommodating their different structural requirements
3Manufacturing precision
If additional mask steps are used for polysilicon resistor formation, then desired configuration is ensured, but time and expense increase
Solution Approach 1:
The patent combines the masking operations for gate structures and resistors into a single unified process. By using the lower surfaces of polysilicon bodies as a common reference plane for both structures, one mask step defines both the gate and resistor configurations simultaneously, eliminating redundant masking steps while ensuring precise configuration alignment
Data Source
AI summary
A structure includes a first gate structure spaced from a second gate structure in a field effect transistor (FET) area of a substrate. A polysilicon resistor is in a space between the first gate structure and the second gate structure. The polysilicon resistor has a lower surface that is farther from the substrate than lower surfaces of the polysilicon bodies of the first and second gate structures. The polysilicon resistor may have a different polarity dopant compared to at least one of the polysilicon bodies of the first and second gate structures.