Self-Aligned Pore Memory Array with Diode Driver
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Solution Overview
Problem
The challenge in manufacturing high-density memory devices is the alignment and size constraints of small dimension structures, which restrict flexibility in design and cause performance variations, especially in self-aligned nonvolatile memory structures based on phase change materials.
Innovation Solution
A memory array structure is developed with self-aligned, pore-type memory elements formed within vias, using a method that includes forming diodes in a dielectric fill material, depositing memory material to fill self-centered openings, and forming top electrodes, allowing for precise control over critical dimensions and high-density integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If small dimension structures are used to increase memory density, then array density is improved, but alignment precision deteriorates due to lithographic tolerance constraints
Solution Approach 1:
The patent employs self-aligned fabrication processes where the pore structures automatically align with the diode contacts through the deposition and patterning of spacer layers. The spacers are formed conformally on the diode structures, ensuring that the pore openings are precisely positioned over the diode contacts without requiring additional alignment steps, thus achieving self-alignment that eliminates manual positioning errors
Solution Approach 2:
The patent transitions from planar 2D memory structures to three-dimensional vertical pore-type structures. By forming pores that extend vertically through the memory stack and filling them with phase change material, the design achieves higher storage density in the vertical dimension while maintaining manufacturability through standard lithographic processes that work in the horizontal plane
2Use of energy by moving object
If the volume of the active region is reduced to minimize reset current, then power consumption is improved, but manufacturing complexity increases due to tighter dimensional control requirements
Solution Approach 1:
The patent applies local quality by creating highly doped regions (P+ and N+) in specific locations within the semiconductor structure. The P+ region is formed at the bottom of the pore and the N+ region at the top, creating localized areas of high carrier concentration that facilitate efficient current injection and extraction while keeping the overall active volume small, thus reducing reset current without requiring complex manufacturing
Solution Approach 2:
The memory cell is segmented into distinct functional regions: the diode contact region, the pore structure filled with phase change material, and the electrode regions. This segmentation allows each component to be optimized independently - the pore volume is minimized for low reset current while the diode and electrode structures are designed for efficient electrical connection, achieving a balance between power consumption and manufacturability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable, high-density memory cell formation with self-aligning and self-converging control, reducing the need for additional lithographic steps and increasing array density by eliminating the need for contact electrodes, thus improving the performance and reliability of phase change memory devices.
Implementation Method 1
Phase change materials, such as chalcogenides, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits.
Implementation Method 2
The small electrode concentrates the current density at the contact point, so that an active region in the phase change material is confined to a small volume near the contact point.
Data Source
AI summary
A memory array with self-centered diode access devices results from a process in which diodes are formed in the fill material, each diode having a lightly-doped first layer of the same conductivity type as the conductive lines; a heavily doped second layer of opposite conductivity type; and a conductive cap. Self-aligned, and self-centered spacers in the self-aligned vias define pores that expose the conductive cap. Memory material is deposited within the pores, the memory material making contact with the conductive cap. A top electrode is formed in contact with the memory material.