Self-Aligned Pore-Type Memory Cell with Diode Access
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Solution Overview
Problem
Manufacturing high-density memory devices with very small dimensions is challenging due to alignment issues and high reset currents required for phase change materials, which hinder the development of efficient nonvolatile memory circuits.
Innovation Solution
The development of fully self-aligned memory cell structures with a diode and dielectric spacer, where the memory element is positioned within an opening defined by the spacer, allowing for a small active region that reduces the current needed for phase change, and the use of thermal isolation to minimize reset current magnitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If very small electrodes are used to reduce contact area and achieve higher current densities, then reset current magnitude is reduced, but manufacturing alignment precision deteriorates
Solution Approach 1:
The dielectric spacer is formed with sidewalls that are self-aligned to the word line, eliminating the need for separate alignment steps. The spacer automatically defines the precise location and dimensions of the memory element contact area, achieving sub-lithographic precision without additional alignment complexity
Solution Approach 2:
The invention transitions from planar electrode contact to a three-dimensional structure where the dielectric spacer extends vertically from the word line surface. This vertical dimension allows precise control of the memory element contact area through spacer height and sidewall profile, independent of lithographic resolution limits
2Use of energy by moving object
If the size of phase change material element is reduced to achieve higher current densities, then reset current magnitude is reduced, but device complexity increases
Solution Approach 1:
The dielectric spacer serves multiple functions simultaneously: it provides thermal isolation to the memory element, defines the precise contact area through its sidewalls, and acts as a structural support. This multi-functionality reduces the need for additional separate components, offsetting the increased structural complexity with functional integration
Solution Approach 2:
The invention applies different material properties to different regions: the dielectric spacer material is selected for low thermal conductivity to provide thermal isolation, while the memory element material is optimized for phase change properties. This localized optimization allows the small memory element to achieve high current density with reduced reset current without requiring the entire device structure to be complex
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density memory arrays with reduced current requirements for phase change, improving the efficiency and density of memory devices by concentrating current density and providing thermal isolation, thus facilitating the production of smaller memory cells.
Implementation Method 1
the use of thermal isolation to minimize reset current magnitude
Implementation Method 2
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current
Implementation Method 3
Each memory cell in the plurality of memory cells comprises a diode comprising doped semiconductor material
Data Source
AI summary
Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells. Each memory cell in the plurality of memory cells comprises a diode comprising doped semiconductor material and a dielectric spacer on the diode and defining an opening, the dielectric spacer having sides self-aligned with sides of the diode. Each memory cell further comprises a memory element on the dielectric spacer and including a portion within the opening contacting a top surface of the diode.