Self-Aligned Interconnect Structure for Shorter Power Rail Routing
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Solution Overview
Problem
The increasing complexity of interconnect structures in semiconductor devices due to rising transistor density leads to issues such as parasitic capacitance, increased resistance, and slower switching speeds, which are exacerbated by the need for complex manufacturing flows that increase the likelihood of manufacturing errors.
Innovation Solution
The implementation of a self-aligned interconnect structure (SIS) that allows for the manufacture of semiconductor devices using a single manufacturing flow, reducing manufacturing complexity and eliminating the need for separate flows for top-to-bottom and bottom-to-top vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate manufacturing flows are used for top-to-bottom and bottom-to-top vias, then manufacturing precision can be maintained, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent merges separate manufacturing flows for top-to-bottom and bottom-to-top vias into a single unified self-aligned interconnect structure manufacturing process. This is achieved by forming both types of vias simultaneously using the same alignment references and processing steps, eliminating the need for separate flows while maintaining precision through self-alignment features.
Solution Approach 2:
The patent creates a universal manufacturing flow that handles both top-to-bottom and bottom-to-top vias using the same process steps and alignment methodology. The self-aligned interconnect structure serves multiple functions: it provides alignment references for both via types, enables simultaneous formation, and maintains precision for all interconnect layers through a single standardized process.
2Loss of energy
If conductive line length is reduced, then resistance and power consumption decrease, but manufacturing precision requirements increase
Solution Approach 1:
The patent establishes alignment references and self-aligned features in advance during the manufacturing process. By pre-defining the positions of conductive lines and vias through self-aligned structures, the system achieves precise alignment without requiring post-manufacturing adjustments, thereby enabling shorter conductive lines while maintaining manufacturing precision.
Solution Approach 2:
The self-aligned interconnect structure uses its own features as alignment references. The structure automatically defines the positions of subsequent layers without requiring external alignment systems, enabling precise placement of shorter conductive lines and reducing dependency on complex external alignment mechanisms.
3Productivity
If transistor density is increased, then device functionality is improved, but parasitic capacitance and interconnect complexity increase
Solution Approach 1:
The patent segments the interconnect structure into self-aligned modules where each segment serves as an alignment reference for the next. This modular segmentation allows for compact routing of conductive lines, reducing the overall length and minimizing parasitic capacitance while supporting high transistor density through efficient space utilization.
4Productivity
If manufacturing flow is simplified, then productivity is improved, but manufacturing precision may deteriorate
Solution Approach 1:
The patent changes the fundamental parameter of alignment methodology from external reference-based to self-aligned. This parameter change enables a single unified manufacturing flow that maintains precision through the inherent self-aligned nature of the interconnect structure, rather than relying on complex external alignment procedures that would require multiple separate flows.
Data Source
AI summary
A device includes a plurality of tracks, wherein at least one of the plurality of tracks comprises a first power rail for a first voltage. The device further includes a first via in electrical contact with the power rail. The device further includes a first contact in electrical contact with the first via. The device further includes a first transistor in electrical contact with the first contact. The device further includes a second transistor in electrical isolation with the first transistor. The device further includes a second contact in electrical contact with the second transistor. The device further includes a second via in electrical contact with the second contact. The device further includes a second power rail in electrical contact with the second via, wherein the second power rail is configured to carry a second voltage.