Self-Aligned Power Via Structure for Scaled MOSFET Power Delivery
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate due to high integration density, leading to performance limitations, and existing technologies struggle to improve performance effectively.
Innovation Solution
The semiconductor device design includes active patterns, source/drain patterns, separation structures, interlayer insulating layers, through-vias, dielectric layers, power vias, and a power delivery network layer to enhance electrical connectivity and reliability, with a focus on self-aligned power via formation to improve integration density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFET sizes are scaled down to increase integration density, then device size is reduced, but operating characteristics deteriorate
Solution Approach 1:
The patent introduces a vertical dimension by forming through-vias that extend from the upper surface to the lower surface of the substrate, and by stacking power delivery network layers above and below the substrate. This three-dimensional power delivery architecture allows power distribution in multiple dimensions, improving electrical characteristics without requiring further lateral scaling of devices.
Solution Approach 2:
The power delivery network is segmented into multiple functional components: through-vias for vertical power transport, upper and lower power delivery network layers for lateral power distribution, and tap cells for local power regulation. This segmentation allows each component to be optimized independently while working together to solve the overall power delivery challenge in scaled devices.
2Productivity
If integration density is increased, then device capacity is improved, but performance deteriorates due to operating characteristic degradation
Solution Approach 1:
The patent transitions from two-dimensional planar power delivery to three-dimensional power delivery by adding through-vias and stacking power network layers. This enables higher integration density while maintaining performance by providing robust power supply through multiple spatial pathways, preventing the performance degradation that normally accompanies increased integration density.
3Reliability
If power delivery network is expanded to improve electrical characteristics, then connectivity is improved, but device complexity increases
Solution Approach 1:
The through-vias serve multiple functions: they provide vertical power transport, act as alignment references for subsequent processing steps, and enable electrical connection between upper and lower power delivery network layers. This multi-functionality reduces the need for separate dedicated structures, thereby limiting complexity growth despite the expanded power delivery capability.
Solution Approach 2:
The dielectric layer is selectively formed on the upper surface before power via formation, creating a preliminary structure that guides and simplifies subsequent via formation. This preliminary action establishes a template that reduces the complexity of the overall power delivery network implementation.
Data Source
AI summary
A semiconductor device includes active patterns on a substrate, source/drain patterns, first and second separation structures, wherein adjacent source/drain patterns are interposed between the first and second separation structures, an interlayer insulating layer on the source/drain patterns and first and second separation structures, a through-via between the adjacent source/drain patterns, penetrating the interlayer insulating layer, and extending toward the substrate, wherein a top of the through-via is coplanar with a top of the interlayer insulating layer, a dielectric layer selectively on the top of the interlayer insulating layer, and opening the top of the through-via, a power via guided to connect to the top of the through-via by the dielectric layer, a power line on the power via and electrically connected to the through-via through the power via, a power delivery network layer on a bottom of the substrate, and a lower conductor under the through-via.