Self-Aligned Etching for ReRAM Bitlines
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Solution Overview
Problem
Conventional ReRAM memory arrays face challenges with high aspect ratio structures and increased costs due to the need for multiple masks and alignment issues during metal bitline patterning, as well as difficulties in filling dielectric material between bitlines to prevent copper extrusion and shorts.
Innovation Solution
A self-aligned etching process is employed using copper bitlines as masks, allowing for a single mask to pattern metal bitlines at a low pitch with low sheet resistance, and a blanket dry etch with high selectivity, which reduces the constraints on filling dielectric material and avoids subsequent metal patterning, thereby simplifying the etching process and reducing the risk of copper extrusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multi-mask patterning is used for metal bitlines, then alignment precision can be maintained, but device complexity and manufacturing cost increase
Solution Approach 1:
The copper bitline structure itself serves as the mask for defining the memory element openings. The bitline material (copper) that needs to be protected is simultaneously used as the masking layer, eliminating the need for separate mask layers and reducing process complexity while maintaining alignment precision.
Solution Approach 2:
The copper bitline layer performs multiple functions: it serves as both the conductive interconnect and the masking layer for defining memory element openings. This multi-functionality reduces the number of process steps and materials needed, simplifying the overall manufacturing process.
2Reliability
If copper bitlines are used to reduce resistance, then electrical performance improves, but risk of copper extrusion and shorts increases
Solution Approach 1:
The potential harmful effect of copper extrusion is converted into a beneficial self-aligned effect. The copper bitline structure is designed to naturally define the mask boundaries, so that the same material that could extrude is precisely controlled to form the alignment reference, turning the risk into a precision mechanism.
Solution Approach 2:
The process design preemptively prevents copper extrusion by using the copper structure itself as the mask boundary. The self-aligned etching process ensures that memory element openings are precisely defined by the copper bitline edges, preventing over-etching and subsequent extrusion issues before they can occur.
3Reliability
If dielectric filling is performed to prevent copper extrusion, then reliability improves, but manufacturing complexity and cost increase
Solution Approach 1:
The copper bitline structure self-defines the boundaries for memory element openings through self-aligned etching, eliminating the need for separate dielectric filling steps to prevent extrusion. The process uses the copper structure's own geometry to control the etching boundaries.
Solution Approach 2:
The harmful step of dielectric filling to prevent copper extrusion is extracted and eliminated from the process. The self-aligned approach using copper as mask inherently prevents extrusion without requiring additional filling materials or steps.
Data Source
AI summary
Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of layers, at least one of which includes a resistive switching material. The stack may be etched using the conductive lines as a mask. As a result, memory elements may be self-aligned to the conductive lines.