Self-Aligned Source/Drain Contacts for Metal Gate Nanotransistors
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Solution Overview
Problem
Forming source and drain regions with desired characteristics in nanostructure transistors is challenging, particularly due to the difficulty in achieving precise alignment and avoiding short circuits with gate metals.
Innovation Solution
A self-aligned process is employed to form source/drain contacts using dielectric spacer layers on sidewalls of engaging gate metals as a mask, allowing for symmetric positioning and relaxed photolithography standards, enabling isotropic etching and prior formation of source/drain isolation structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography alignment methods are used to form source and drain contacts, then alignment precision can be achieved, but the process complexity increases and short circuits with gate metals may occur
Solution Approach 1:
The dielectric spacer layer automatically forms on the sidewalls of the gate metal structure through conformal deposition, creating a self-aligned mask that defines the source/drain contact regions. This self-service mechanism eliminates the need for separate photolithography alignment steps, reducing process complexity while maintaining precise alignment through the inherent geometry of the spacer layer formation
Solution Approach 2:
The dielectric spacer layer acts as an intermediary mask structure between the gate metal and the source/drain contact formation process. This intermediary element provides the alignment reference without requiring direct photolithographic patterning of the contact regions, simplifying the overall process while ensuring precise positioning
2Manufacturing precision
If conventional hard mask processes are used for source/drain contact formation, then alignment can be controlled, but the number of process steps increases
Solution Approach 1:
The dielectric spacer layer is formed in advance on the gate metal sidewalls before the source/drain contact etching process. This preliminary action creates the alignment mask structure that guides subsequent contact formation, eliminating the need for separate hard mask deposition and patterning steps, thereby improving productivity without sacrificing alignment control
Solution Approach 2:
The alignment mask function is merged with the dielectric spacer layer that is already present on the gate metal structure. Instead of using a separate hard mask layer, the spacer layer serves dual purposes as both the structural element and the alignment reference, reducing the total number of process steps while maintaining precise alignment control
3Shape
If anisotropic etching is used for source/drain contact formation, then vertical profiles can be achieved, but alignment precision may be compromised
Solution Approach 1:
The dielectric spacer layer on the gate metal sidewalls serves as a self-aligned etch mask that automatically defines the source/drain contact boundaries. This self-service mechanism ensures that the contact regions are precisely positioned relative to the gate structure, maintaining alignment precision while enabling the use of isotropic etching processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves wafer yields and electrical performance by avoiding short circuits, reducing photolithography complexity, and ensuring better alignment of source/drain contacts, resulting in integrated circuits with enhanced functionality.
Implementation Method 1
a dielectric spacer layer is formed on a sidewall of the gate metal
Implementation Method 2
a dielectric spacer layer is formed on a sidewall of the gate metal
Implementation Method 3
forming a U-shaped recess in the source/drain region with an etching process using the dielectric spacer layer as a self-aligned mask
Data Source
AI summary
An integrated circuit includes a first transistor having a plurality of stacked channels and a source/drain region in contact with the stacked channels of the first transistor. The integrated circuit includes a second transistor including a plurality of stacked second channels in contact with the source/drain region and a second gate metal above the second channels. A dielectric spacer layer is positioned on sidewalls of the first and second gate metal. A recess is formed in the source/drain region in a self-aligned manner utilizing the dielectric spacer layer as a mask. A source/drain contact is formed in the recess equidistant between the first gate metal and the second gate metal.