Self-aligned select gate cut for 3D NAND memory
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Solution Overview
Problem
Current 3D-NAND devices suffer from memory hole losses during the select gate cut process, which reduces the number of available memory holes and storage capacity due to the destruction of at least one memory hole for each cut line, leading to inefficiencies as device node sizes decrease and more memory holes are packed into the same space.
Innovation Solution
A non-destructive self-aligned select gate cut process is implemented, where a dielectric filled cut line separates memory hole lines without disabling the functionality of any memory holes, allowing for staggered memory hole configurations and minimizing losses by using a stack of alternating silicon and nitride layers with memory holes filled with core oxide and semiconductor material, and a conductive material surrounding the holes to maintain their functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cut line is formed to separate memory hole lines for bit line access, then memory hole lines are properly separated for electrical isolation, but at least one memory hole is destroyed in each cut line location
Solution Approach 1:
The memory hole lines are segmented by forming cut lines between them. The invention divides the continuous structure into discrete segments (memory holes) separated by dielectric-filled regions, enabling independent electrical isolation while preserving the functional integrity of each segment.
Solution Approach 2:
A dielectric material is introduced as an intermediary substance in the cut line regions. This dielectric filler acts as a mediator that provides the necessary electrical isolation between adjacent memory hole lines without requiring the destruction of memory holes, replacing the traditional approach of removing material entirely.
2Quantity of substance
If more memory holes are packed into the same space to increase storage capacity as node size decreases, then storage density is improved, but the proportion of memory holes lost to cut lines increases
Solution Approach 1:
The invention changes the physical state and composition of the cut line regions by filling them with dielectric material instead of leaving them as voids or removing material completely. This parameter change allows for more aggressive scaling and denser memory hole packing while minimizing functional loss.
Solution Approach 2:
The invention converts the potentially harmful effect of cut lines (which traditionally destroy memory holes) into a beneficial structure by filling the cut line regions with dielectric material. This transforms the cut line from a source of memory hole loss into a functional element that provides isolation while preserving adjacent memory holes.
3Reliability
If traditional cut lines are used to provide separation between memory hole lines, then electrical isolation is achieved, but storage efficiency is reduced due to memory hole destruction
Solution Approach 1:
The dielectric-filled cut line structure serves multiple functions simultaneously: it provides electrical isolation between memory hole lines, maintains mechanical structural integrity, and preserves the functionality of adjacent memory holes. This multi-functional approach eliminates the trade-off between isolation and efficiency.
Solution Approach 2:
The dielectric material acts as an intermediary that enables electrical isolation without the need to destroy memory holes. It fills the space where traditional cut lines would remove material, providing the necessary isolation while allowing memory holes to remain intact and functional.
Data Source
AI summary
Electronic devices and methods of forming the electronic devices are described. The electronic devices comprise a plurality of memory holes extending along a first direction through a plurality of alternating oxide and nitride layers. Each memory hole has a core oxide surrounded by a semiconductor material, the semiconductor material surrounded by a dielectric. The memory holes are staggered to provide a plurality of memory hole lines having spaced memory holes so that adjacent memory hole lines have the memory holes in a staggered configuration. A conductive material is on top of the stack of alternating oxide and nitride layers. A dielectric filled cut line extends through the conductive material in a direction across the plurality of memory hole lines. The dielectric filled cut line separates a first memory hole line from an adjacent second memory hole line without disabling the functionality of the memory holes.