Self-Aligned Select Gates for Split-Gate Flash Read Margin
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Solution Overview
Problem
In split-gate flash memory cells, even-odd bitline reading current (Ir1) variations due to select gate critical dimension (CD) misalignment and process variations lead to threshold voltage (Vt) differences, reducing read margin and circuit design margins.
Innovation Solution
A self-aligned select gate patterning process using anisotropic plasma etching forms spacer-shaped select gates, eliminating CD misalignment and reducing Ir1 variations through self-alignment to the FG-CG stacks without additional masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional photolithography alignment is used to form select gates, then the fabrication process is simple, but critical dimension misalignment occurs between even and odd select gates causing Ir1 variation
Solution Approach 1:
The patent performs preliminary patterning of the control gate and floating gate structures before forming the select gates. By pre-forming these reference structures, the select gates can be self-aligned to them, eliminating photolithography misalignment issues. The select gates are formed using spacer deposition and etching that automatically aligns them to the pre-existing control gate edges, ensuring consistent critical dimensions across even and odd select gates.
Solution Approach 2:
The patent implements self-aligned patterning where the select gates automatically align themselves to the control gate structures through spacer formation. The spacer width, controlled by conformal deposition thickness, directly determines the select gate critical dimension. This self-service mechanism eliminates the need for separate alignment steps and ensures manufacturing precision without complicating the overall fabrication process.
2Adaptability or versatility
If select gate CD varies due to process variations, then manufacturing flexibility is maintained, but threshold voltage differences increase reducing read margin
Solution Approach 1:
The patent changes the critical parameter from photolithography-defined CD to deposition-thickness-defined CD. By controlling the spacer deposition thickness uniformly across the wafer, the select gate critical dimension is precisely controlled. This parameter change makes the process less sensitive to typical photolithography variations and improves threshold voltage consistency, thereby enhancing read margin while maintaining adaptability through controllable deposition parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Minimizes even-odd BL Ir1 variations across the die and wafer, enhancing read margin and circuit design reliability by stabilizing select gate CD and Vt distributions.
Implementation Method 1
A self-aligned select gate patterning process using anisotropic plasma etching forms spacer-shaped select gates
Data Source
AI summary
An integrated circuit includes first and second gate stacks located over a dielectric layer that is in turn disposed over a semiconductor substrate. Each gate stack includes a floating gate located on the dielectric layer and a control gate located over the floating gate. A first select gate electrode is located on a side of the first gate stack and a second select gate electrode is located on a side of the second gate stack. The first and second select gate electrodes have adjacent sidewalls, each adjacent sidewall having a rounded top corner. The gate stacks may be portions of a split gate memory cell.