Self-aligned Source and Drain Contacts via Silicide Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor device dimensions scale down, non-self-aligned contact (SAC) processes face challenges in maintaining low contact resistance, making improved contact designs and fabrication techniques necessary.
Innovation Solution
The development of self-aligned semiconductor field-effect transistor (FET) device source and drain contacts, achieved through the formation of a silicide layer between lower and upper contacts, which are offset by gate spacers, allowing for SAC alignment without the complexity of traditional SAC patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If non-self-aligned contact processes are used, then ease of manufacture and cost are improved, but contact resistance increases as device dimensions scale down
Solution Approach 1:
The silicide layer automatically forms a self-aligned barrier between the upper and lower contacts through thermal diffusion during annealing. The silicide forms only in regions where the silicon layer contacts the lower contact metal, creating self-aligned contact structures without requiring complex self-aligned patterning processes. This achieves low contact resistance while maintaining process simplicity.
Solution Approach 2:
A silicide layer is introduced as an intermediary between the upper and lower contacts. This silicide layer acts as a mediator that reduces contact resistance while maintaining the simplicity of non-self-aligned processes. The silicide forms through thermal annealing of a deposited silicon layer, creating a low-resistance pathway without requiring complex patterning.
2Reliability
If self-aligned contact patterning processes are used, then contact resistance is reduced, but device complexity and fabrication cost increase
Solution Approach 1:
The silicide layer automatically forms a self-aligned barrier between the upper and lower contacts through thermal diffusion during annealing. The silicide forms only in regions where the silicon layer contacts the lower contact metal, creating self-aligned contact structures without requiring complex self-aligned patterning processes. This achieves low contact resistance while maintaining process simplicity.
Solution Approach 2:
The complex self-aligned patterning steps are extracted and replaced with a simpler silicide formation process. Instead of using multiple lithography and etching steps to achieve self-alignment, the patent extracts the alignment function to the silicide formation step, where the silicide naturally forms only in contact regions through thermal diffusion.
3Area of moving object
If device dimensions are scaled down, then device density is improved, but maintaining low contact resistance becomes more difficult with non-SAC processes
Solution Approach 1:
The patent changes the physical and chemical parameters of the contact structure by introducing a silicide layer formed through controlled thermal annealing. By adjusting annealing temperature, time, and silicon layer thickness, the silicide forms with optimal properties for reduced contact resistance in scaled devices, maintaining reliability as device dimensions decrease.
Solution Approach 2:
A silicide layer is introduced as an intermediary between the upper and lower contacts. This silicide layer acts as a mediator that reduces contact resistance while maintaining the simplicity of non-self-aligned processes. The silicide forms through thermal annealing of a deposited silicon layer, creating a low-resistance pathway without requiring complex patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach leverages the cost-effectiveness of non-SAC processes while achieving self-aligned contact designs, reducing contact resistance and maintaining device performance as device dimensions scale down.
Implementation Method 1
annealing the device structure under conditions sufficient to form a silicide directly on the lower source and drain contacts
Data Source
AI summary
Self-aligned semiconductor FET device source and drain contacts and techniques for formation thereof are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate; gate spacers offsetting the at least one gate from the source and drains; lower source and drain contacts disposed on the source and drains; upper source and drain contacts disposed on the lower source and drain contacts; and a silicide present between the lower source and drain contacts and the upper source and drain contacts.