Self-Aligned Silicide Contacts for High Voltage FETs
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Solution Overview
Problem
High voltage field effect transistors often suffer from surface breakdown voltage due to complex extended low doped drain (LDD) structures, which increase process complexity and cost.
Innovation Solution
A semiconductor structure with a field effect transistor comprising a doped well, gate dielectric, gate electrode, and a dielectric capping mask with vertically- and horizontally-extending portions, along with source- and drain-side openings, allowing for self-aligned silicide contacts to reduce contact resistance and junction leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex extended low doped drain (LDD) structures are used to improve surface breakdown characteristics, then surface breakdown voltage is improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the complex extended LDD structure from the device design. Instead of using the traditional complex LDD approach, the invention employs a simplified structure with a dielectric capping mask that has vertically-extending and horizontally-extending portions, eliminating the need for complex extended low doped drain regions while maintaining surface breakdown protection.
Solution Approach 2:
The dielectric capping mask is segmented into distinct functional portions: vertically-extending portions that laterally surround the gate electrode and horizontally-extending portions that contact the gate dielectric. This segmentation allows each portion to perform its specific function independently, providing surface breakdown protection without requiring complex LDD structures.
2Reliability
If complex extended low doped drain (LDD) structures are used to improve surface breakdown characteristics, then surface breakdown voltage is improved, but manufacturing cost increases
Solution Approach 1:
The patent removes the complex extended LDD structure that drives up manufacturing costs. The simplified design using a dielectric capping mask with specific geometric portions reduces the number of fabrication steps and materials required, thereby lowering manufacturing cost while maintaining reliability.
Solution Approach 2:
The dielectric capping mask serves multiple functions simultaneously: it provides surface breakdown protection, defines contact regions, and structures the device architecture. This multi-functionality eliminates the need for separate complex LDD structures, reducing manufacturing complexity and cost.
3Reliability
If self-aligned silicide contacts are formed using the dielectric capping mask structure, then contact resistance is reduced, but device structure complexity increases
Solution Approach 1:
The dielectric capping mask structure enables self-aligned formation of silicide contacts. The vertically-extending and horizontally-extending portions of the mask automatically define the contact regions, allowing silicide to form in the correct locations without additional alignment steps. This self-alignment reduces contact resistance while avoiding the complexity of multi-step alignment processes.
Solution Approach 2:
The dielectric capping mask is formed beforehand with pre-defined openings and extending portions that predetermine the exact locations where silicide contacts will form. This preliminary structuring ensures proper alignment and reduces contact resistance without requiring complex in-situ alignment during subsequent processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively addresses surface breakdown voltage issues by lowering contact resistance and junction leakage, simplifying the process while maintaining high voltage performance.
Implementation Method 1
a first source-side metal-semiconductor alloy portion contacting a top surface of the first source region and located within the source-side opening; and a first drain-side metal-semiconductor alloy portion contacting a top surface of the first drain region and located within the drain-side opening
Implementation Method 2
a dielectric capping mask overlying the first doped well, wherein the dielectric capping mask comprises a vertically-extending portion that laterally surrounds the first gate electrode, a top portion that overlies a peripheral region of a top surface of the first gate electrode, and a horizontally-extending portion that contacts a top surface of the first gate dielectric outside an area of the first gate electrode
Data Source
AI summary
A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.