Self-Aligned Silicide Gate in Shielded-Gate Trench MOSFETs
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Solution Overview
Problem
Shielded-gate trench power MOSFETs face high gate resistance and manufacturing challenges due to small trench pitch and surface topology, making them unsuitable for rapid switching applications, and conventional silicide mask implementation is difficult.
Innovation Solution
A self-aligned gate poly silicide process is integrated into shielded-gate trench power MOSFETs, avoiding high-temperature processing after silicide deposition to maintain silicide quality, using low-temperature interlayer dielectrics and avoiding additional masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicide mask implementation is used, then gate resistance can be reduced, but manufacturing complexity increases due to additional masking steps and difficulty with small trench pitch
Solution Approach 1:
The gate oxide layer serves a dual function: as the insulating layer between gate and channel, and as a self-aligned mask for silicide deposition. The silicide is deposited directly over the gate region where the gate oxide is present, automatically defining the silicide pattern without requiring separate photolithography masking steps. This self-alignment mechanism eliminates the need for precise mask alignment in small trench pitch structures.
Solution Approach 2:
The gate oxide layer performs multiple functions simultaneously: electrical insulation between gate and semiconductor channel, and pattern definition mask for silicide formation. This multi-functionality reduces the total number of process steps and eliminates the need for dedicated mask layers, simplifying the manufacturing process while achieving low gate resistance through silicide formation.
2Productivity
If high-temperature processing is applied after silicide deposition, then subsequent process steps can be completed, but silicide quality degrades
Solution Approach 1:
All high-temperature processing steps required for device formation are completed before silicide deposition. The silicide is deposited as a final or near-final step, protecting it from thermal degradation. This preliminary completion of thermal processes ensures silicide quality is maintained while still allowing necessary device fabrication steps to occur.
Solution Approach 2:
The processing temperature sequence is inverted from conventional approaches: instead of depositing silicide early and subjecting it to high temperatures, the silicide deposition is scheduled for lower-temperature conditions after all high-temperature processing is complete. This parameter change in processing sequence protects silicide crystalline structure and electrical properties from thermal degradation.
Data Source
AI summary
Apparatus and methods for shielded-gate trench power MOSFETs are disclosed herein. The power MOSFETs are fabricated using a self-aligned gate poly silicide to achieve low gate resistance. Accordingly, the power MOSFETs can be used in high speed applications operating with fast transistor switching speeds. Moreover, the self-aligned gate poly silicide processing can be achieved in relatively few processing steps, and thus can avoid the cost and/or complexity associated with conventional silicidation techniques for trench power MOSFETs. In particular, silicidation can include applying a silicide that is self-aligned to a gate oxide without an additional mask.