Self-Aligned Silicide in Vertical Gate All Around Devices
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Solution Overview
Problem
In the development of vertical gate all around (VGAA) transistors, existing methods face challenges in reducing contact resistance and parasitic resistance due to the limited surface area of silicide regions and their distance from the nanowire channel region.
Innovation Solution
A self-aligned silicide region is formed in the upper portion of the bottom source/drain region before the interlayer dielectric and contact formation, increasing the silicide's surface area and spacing it closer to the nanowire, thereby reducing contact and parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional silicide region formation method is used in VGAA devices, then the fabrication process is simpler, but the contact resistance and parasitic resistance are higher due to limited surface area and greater distance from the nanowire channel region
Solution Approach 1:
The silicide region is formed before the interlayer dielectric and contact formation steps, allowing the silicide to be positioned closer to the nanowire channel region. This preliminary action enables the silicide region to have greater surface area for charge carrier transport while reducing parasitic resistance, as the silicide is formed in the upper portion of the source/drain region before subsequent processing steps
2Reliability
If the silicide region is positioned farther from the nanowire channel region, then the fabrication alignment is easier, but the parasitic resistance increases due to longer charge carrier transport path
Solution Approach 1:
The silicide region is self-aligned to the gate structure through the formation process, where the silicide automatically positions itself in the upper portion of the source/drain region. This self-alignment mechanism eliminates the need for separate alignment steps while ensuring the silicide is positioned as close as possible to the nanowire channel region, thereby reducing parasitic resistance without compromising fabrication precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances yield and lowers contact resistance while reducing parasitic resistance in VGAA transistors by increasing the silicide's surface area and proximity to the nanowire channel region.
Implementation Method 1
A self-aligned silicide region may be formed in an upper portion of the bottom source/drain region after the gate structure but before a corresponding interlayer dielectric (ILD) or contact to the bottom source/drain region are formed. Thus, the silicide region can be formed to have a greater surface area than a subsequently formed contact, advantageously reducing contact resistance.
Implementation Method 2
the resulting silicide region may be spaced closer to the nanowire (e.g., the channel region), which also advantageously reduces parasitic resistance
Data Source
AI summary
An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the source/drain region. The source/drain region further extends into the semiconductor substrate past edges of the nanowire. The semiconductor device further includes a gate structure encircling the channel region and a silicide in an upper portion of the source/drain region. A sidewall of the silicide is aligned with a sidewall of the gate structure.