Self-Aligned Backside Source Contact for Overlay-Tolerant Transistors
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Solution Overview
Problem
The formation of backside contact structures in multi-gate transistors, such as FinFETs and MBC transistors, is challenged by overlay variations leading to potential short circuits between the backside source contact and the gate structure, making it difficult to achieve precise alignment without defects.
Innovation Solution
A self-aligned backside contact structure is implemented using a bottom self-aligned contact dielectric layer that covers the backsides of the source feature and gate structure, allowing selective access to the source feature, thereby aligning the formation of backside source contact openings without high overlay precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional backside contact structures are used in multi-gate transistors, then the gate structure can provide good channel control, but overlay variations cause misalignment between backside source contact openings and source features, leading to device defects
Solution Approach 1:
A bottom self-aligned contact dielectric layer is formed over the substrate before the gate structure is created. This layer extends into the source region and provides a pre-positioned alignment reference that guides subsequent contact opening formation, ensuring precise alignment without requiring high overlay precision during later processing steps
Solution Approach 2:
The bottom self-aligned contact dielectric layer acts as an intermediary structure between the substrate and the gate structure. It provides a physical reference that mediates the alignment between backside source contact openings and source features, eliminating the need for precise overlay alignment between separate processing layers
Data Source
AI summary
A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.