Self-Aligned Source/Drain Extensions in III-V FinFETs
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Solution Overview
Problem
In compound fin field effect transistors (finFETs), the presence of a gate spacer complicates the formation of source/drain extension regions with sufficient overlap over the gate electrode, leading to reduced performance due to insufficient overlay, particularly in III-V compound finFETs.
Innovation Solution
A method involving the formation of a gate stack with a gate dielectric and electrode over compound semiconductor fins, followed by epitaxial deposition of source/drain extension regions that are self-aligned to the gate stack's sidewalls, ensuring sufficient overlap and the creation of raised source and drain regions for a low-resistance path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ion implantation is used to form source/drain extension regions, then the manufacturing process is simple, but the overlay between source/drain extension regions and gate electrode is insufficient
Solution Approach 1:
The patent introduces gate spacers as intermediary structures that are formed first, then used as etch masks to define the source/drain extension regions. This intermediary structure enables precise alignment and overlay between the extension regions and gate electrode, resolving the precision issue while maintaining process simplicity through self-aligned fabrication steps.
Solution Approach 2:
The gate spacers are formed in advance before the source/drain extension regions. This preliminary action establishes the precise positional reference for subsequent epitaxial growth, ensuring that the extension regions will automatically achieve the required overlay with the gate electrode without requiring complex alignment procedures.
2Manufacturing precision
If gate spacer is present in finFET, then gate structure is well-defined, but source/drain extension regions cannot achieve sufficient overlap with gate electrode
Solution Approach 1:
The patent utilizes the vertical dimension by forming raised source and drain regions that extend upward from the substrate surface. This three-dimensional structure allows the extension regions to achieve sufficient overlap with the gate electrode in the lateral direction while the gate spacer maintains precise gate definition, thereby resolving the contradiction between structural precision and device performance.
Solution Approach 2:
The patent creates different fin width configurations in different regions: narrower fin portions adjacent to the gate electrode for optimal electric field control, and wider fin portions in other areas for mechanical strength. This local variation in geometry allows the device to achieve both precise gate definition and sufficient extension region overlap for high performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures a sufficient overlap between source/drain extension regions and the gate electrode, enhancing the performance of III-V compound finFETs by providing a low-resistance path and improving on-current.
Implementation Method 1
The at least one compound semiconductor fin is thinned employing the gate stack as an etch mask
Implementation Method 2
Source/drain extension regions are epitaxially deposited on physically exposed surfaces of the at least one semiconductor fin
Implementation Method 3
A source-side fin portion and a drain-side fin portion that have a second width are formed. A source-extension region and a drain-extension region are simultaneously formed on the source-side fin portion and on the drain-side fin portion, respectively, by selective epitaxy of a doped compound semiconductor material
Data Source
AI summary
A gate stack including a gate dielectric and a gate electrode is formed over at least one compound semiconductor fin provided on an insulating substrate. The at least one compound semiconductor fin is thinned employing the gate stack as an etch mask. Source/drain extension regions are epitaxially deposited on physically exposed surfaces of the at least one semiconductor fin. A gate spacer is formed around the gate stack. A raised source region and a raised drain region are epitaxially formed on the source/drain extension regions. The source/drain extension regions are self-aligned to sidewalls of the gate stack, and thus ensure a sufficient overlap with the gate electrode. Further, the combination of the source/drain extension regions and the raised source/drain regions provides a low-resistance path to the channel of the field effect transistor.