Self-aligned stack gate structure for non-volatile memory arrays
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Solution Overview
Problem
Existing stack gate structures in non-volatile memory arrays face challenges in efficiently isolating and positioning charge holding gates and control gates, leading to suboptimal charge storage and control over current flow between conductivity type regions.
Innovation Solution
A stack gate structure is developed with a semiconductor substrate featuring parallel active regions, where each stack gate structure includes a charge holding gate covered by insulating materials and a control gate with additional insulating layers, allowing for precise control over charge storage and current flow through a method involving multiple deposition and etching steps to form planarized, self-aligned gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional stack gate structures are used with separate positioning methods for charge holding gate and control gate, then manufacturing process complexity increases, but manufacturing precision deteriorates due to alignment difficulties
Solution Approach 1:
The patent merges the positioning functions for both the charge holding gate and control gate into a single etch stop layer. This layer is formed once and serves as the reference for positioning both gates sequentially, eliminating the need for separate positioning structures and reducing alignment steps while maintaining high precision
Solution Approach 2:
The etch stop layer is formed in advance before both the charge holding gate and control gate are positioned. This preliminary structure establishes the positioning reference early in the process, enabling subsequent gates to be aligned accurately without requiring complex real-time alignment procedures
2Manufacturing precision
If multiple separate positioning structures are used for charge holding gate and control gate, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
Instead of using separate positioning structures for the charge holding gate and control gate, the patent combines both positioning functions into a single etch stop layer. This unified approach reduces structural complexity while maintaining the ability to precisely position both gates through sequential etching processes that reference the same positioning layer
3Manufacturing precision
If conventional deposition and etching steps are used without self-alignment, then ease of manufacture improves, but manufacturing precision deteriorates
Solution Approach 1:
The etch stop layer serves itself as the positioning reference for both the charge holding gate and control gate. By using the same layer that defines the charge holding gate position to also define the control gate position, the structure self-aligns the gates relative to each other, achieving high precision without requiring additional external alignment procedures
Solution Approach 2:
The etch stop layer is created in advance to establish the geometric reference for subsequent gate formation. This preliminary positioning structure enables the charge holding gate and control gate to be self-aligned through sequential etching processes, maintaining fabrication simplicity while achieving high precision charge storage
Data Source
Figure 1~2C
Figure 3A~3C
Figure 4A~5B-2
AI summary
A stack gate structure for use in a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions. Stack gate structures are formed over active regions, and each includes a first insulating material is between each stack gate structure in the second direction perpendicular to the first direction, a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, a first portion of a control gate over the third insulating material, a second portion of the control gate is over the top surface of the first portion of the control gate and over the top surface of the first insulating material adjacent thereto and extending in the second direction and a fourth insulating material is over the second portion of the control gate.