Self Aligned Stud Bump Passivation for Microelectronics
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Solution Overview
Problem
Conventional microelectronic packaging methods require multiple masking steps and have high overlay tolerances, leading to increased complexity and potential for errors in forming copper bumps, especially when the passivation layer is formed before the stud bump, limiting the thickness and protection of the bump structure.
Innovation Solution
A self-aligned stud bump formation method where the stud bump is created prior to the passivation layer, reducing the number of patterning operations and overlay tolerances, and using a passivation layer to encapsulate the seed layer and bump, providing protection and mechanical reinforcement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the passivation layer is formed prior to the copper bump, then the chip structure is protected early in the manufacturing process, but the manufacturing process complexity increases and overlay tolerance requirements become more stringent
Solution Approach 1:
The passivation layer is formed in advance before the copper bump creation process, providing early protection to the chip structure. This preliminary action allows the passivation layer to serve as a protective barrier during subsequent manufacturing steps, reducing the need for additional protective measures and simplifying the overall process.
Solution Approach 2:
The passivation layer acts as an intermediary element between the chip substrate and the copper bump formation process. It provides a controlled interface that manages the interaction between the substrate and the bump formation process, enabling better process control and reduced overlay tolerance requirements.
2Reliability
If the passivation layer is formed prior to the copper bump, then early protection is provided, but the overlay tolerance requirements increase leading to higher potential for errors
Solution Approach 1:
The passivation layer is formed in advance to establish a stable reference structure before copper bump creation. This preliminary formation provides a well-defined surface that simplifies subsequent alignment operations, effectively reducing the stringent overlay tolerance requirements that would otherwise be necessary.
3Reliability
If multiple masking steps are used in conventional methods, then the copper bump formation is achieved, but the manufacturing process complexity and time increase
Solution Approach 1:
The patent combines multiple discrete masking steps into an integrated process where the passivation layer formation serves dual purposes: providing protection and establishing alignment references for subsequent copper bump formation. This merging of functions reduces the total number of separate masking operations required, thereby decreasing manufacturing process time.
Solution Approach 2:
The passivation layer is designed to serve multiple functions simultaneously: it provides structural protection, acts as an alignment reference for copper bump formation, and facilitates the overall manufacturing process. This multi-functionality eliminates the need for separate dedicated masking steps, reducing both process complexity and time.
4Reliability
If the passivation layer is formed prior to the copper bump, then early protection is provided, but the thickness and protection of the bump structure are limited
Solution Approach 1:
The passivation layer is formed in advance to provide initial protection and establish a stable foundation. This early protection allows subsequent copper bump structures to be built with greater thickness and enhanced protection without compromising the underlying chip structure, as the passivation layer already provides a protective base layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces overlay tolerance by up to 20 microns, simplifies the manufacturing process, enhances protection against corrosion and moisture, and allows for thinner chip substrates with flexible implementation on packages or PCB systems, while maintaining mechanical integrity.
Implementation Method 1
A first photoresist layer is formed on the substrate, and patterned to create a first opening
Implementation Method 2
A metal layer may then be electroplated into the first opening
Data Source
AI summary
A method of fabricating multiple conductor layers utilizing the same seed layer is described. In an embodiment a stud bump structure is described in which the seed layer is encapsulated by the passivation layer. By forming the stud bump prior to the passivation layer, the height of the stud bump extending from the top surface of the passivation layer can be controlled.