Thin-Film Transistor Patterning With Self-Aligned Gate and Contacts
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Solution Overview
Problem
The manufacturing of thin-film transistors faces challenges in achieving accurate alignment between gate and source/drain terminals, particularly on large-area substrates, leading to misalignments and performance degradation due to imperfections in interfaces and limitations in device feature size and density.
Innovation Solution
A method involving the formation of a depression in a resist material covering a substrate to define the positions of source, drain, and gate terminals in a single step, allowing for correct alignment and deposition of semiconductive, dielectric, and conductive layers, with undercutting and widening techniques to enhance electrical contact and interface quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithographic techniques with multiple masks are used to manufacture TFTs, then the relative positions of source, drain, and gate terminals can be defined, but alignment errors occur between finely patterned masks at different stages
Solution Approach 1:
The patent combines multiple alignment functions into a single mask structure. The mask includes a first region defining source/drain terminal positions and a second region defining gate terminal positions, both aligned relative to a common reference feature on the substrate. This single-mask approach eliminates alignment errors between multiple mask stages while maintaining the ability to define all terminal positions accurately.
Solution Approach 2:
The patent establishes reference features on the substrate before applying the mask. These reference features are formed in advance to provide alignment targets that ensure correct positioning of both source/drain and gate terminals relative to each other and to the substrate, eliminating the need for complex multi-stage mask alignment.
2Area of stationary object
If the substrate area is increased to accommodate large-area devices, then the display area is expanded, but local misalignments occur between source/drain and gate due to substrate imperfections and distortions
Solution Approach 1:
The patent implements local reference features distributed across the substrate surface rather than relying on global alignment. Each mask is positioned relative to local reference features that are formed directly on the substrate, compensating for local distortions and imperfections. This allows large-area substrates to maintain alignment precision despite variations across the surface.
3Quantity of substance
If the minimum device feature size is reduced to increase device density, then the resolution of displays is improved, but manufacturing limitations prevent accurate formation of nanoscale features
Solution Approach 1:
The patent uses a mask that directly copies the desired terminal pattern onto the substrate through a single exposure step. The mask contains precisely defined regions for source/drain and gate terminals that are transferred to the substrate in one action, avoiding the cumulative errors that would occur in multi-stage lithography. This enables accurate formation of nanoscale features at high density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures precise alignment and improved electrical contact between terminals, reducing misalignments and enhancing the performance and density of thin-film transistors, suitable for large-area devices and nanoscale features.
Implementation Method 1
forming at least one depression in a surface of the covering of resist material, the at least one depression extending over a first portion of the region, the first portion separating a second portion of the region from a third portion of the region
Implementation Method 2
depositing semiconductive material at least inside the window to form a layer of semiconductive material connecting the second portion to the third portion
Implementation Method 3
depositing dielectric material to form a layer of dielectric material over said layer of semiconductive material
Implementation Method 4
depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material
Data Source
Figure 1a~1d
Figure 1e~1h
Figure 2a~2d
AI summary
A method of manufacturing a transistor comprises: providing a substrate and a region of electrically conductive material supported by the substrate; forming at least one layer of resist material over said region to form a covering of resist material over said region; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region, said first portion separating a second portion of the region from a third portion of the region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a portion of substrate separating the second portion from the third portion of the region; depositing semiconductive material at least inside the window to form a layer of semiconductive material connecting the second portion to the third portion; depositing dielectric material to form a layer of dielectric material over said layer of semiconductive material; depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material; and removing resist material at least from around said window so as to expose the second and third portions, whereby said second and third portions provide a source terminal and a drain terminal respectively and the layer of electrically conductive material provides a gate terminal to which a potential may be applied to control a conductivity of the layer of semiconductive material connecting the second and third portions. In another aspect, the method begins with separate source and drain terminals provided on a common substrate. Corresponding transistors, logic gates, arrays, and electronic circuits are described.