Self-aligned top via protective structure
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Solution Overview
Problem
Subtractive patterning processes in semiconductor device fabrication often result in damage to lower level vias due to misalignment issues, leading to reliability and resistance concerns.
Innovation Solution
A self-aligned subtractive patterning scheme is implemented, where protective structures such as conductive cap layers or liners are formed on lower level vias to mitigate damage during the patterning process, using materials with an etch rate less than or equal to that of the vias, allowing for the formation of upper level conductive lines and vias with relaxed alignment tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If subtractive patterning process is used to form upper level conductive lines, then resistance benefits and lack of conductive liner requirement are achieved, but damage to lower level vias occurs due to misalignment
Solution Approach 1:
A protective structure consisting of a protective layer and conductive cap layer is introduced as an intermediary between the lower level via and the subtractive patterning process. The protective layer has etch selectivity relative to the lower level via material, allowing it to be removed selectively after patterning, while the conductive cap layer protects the via during the process and provides post-patterning via protection.
Solution Approach 2:
The protective structure is formed in advance before the subtractive patterning process. The protective layer is deposited conformally over the lower level via, and the conductive cap layer is formed selectively on the via top surface, preparing the via for protection before the damaging patterning step occurs.
2Object-affected harmful factors
If protective structures are added to protect lower level vias, then via damage is mitigated, but process complexity increases
Solution Approach 1:
The protective layer is deposited conformally to automatically conform to the via geometry, and the conductive cap layer is formed selectively on the via top surface through self-aligned processes. The protective structure serves multiple functions simultaneously: protecting during patterning, defining alignment, and providing post-patterning protection, reducing the need for additional separate process steps.
Solution Approach 2:
The protective structure performs multiple functions: (1) protects lower level via during subtractive patterning, (2) provides etch selectivity reference for alignment, (3) serves as a mask for conductive cap layer formation, and (4) provides ongoing via protection after patterning. This multi-functionality reduces overall process complexity despite adding initial structure formation steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents damage to lower level vias, reducing reliability and resistance concerns by ensuring minimal damage during subtractive patterning, enabling the formation of self-aligned top vias with improved reliability and performance.
Implementation Method 1
The protective structure includes a material having an etch rate less than or equal to that of the lower level via
Data Source
AI summary
A semiconductor device includes a base structure including a lower level via and a lower level dielectric layer, a conductive pillar including an upper level line and an upper level via disposed on the lower level via, and a protective structure disposed between the lower level via and the upper level line. The protective structure includes a material having an etch rate less than or equal to that of the lower level via.