Self-Aligned Top Via Formation via Conductive Hardmask Segmentation
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Solution Overview
Problem
In semiconductor device fabrication, lithographic alignment of vias and conductive lines can result in overlay and alignment errors, leading to critical dimension variation and issues with via contact resistance and dielectric barriers, particularly at small dimensions.
Innovation Solution
The method involves forming recessed odd and even hardmasks with different materials, followed by the deposition of conductive hardmasks with a semicircle cross-sectional shape, to create self-aligned top vias at line ends, thereby controlling via critical dimension and reducing alignment-related fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithographic alignment is used for via and conductive line formation, then manufacturing process is simple, but alignment errors cause via critical dimension variation and contact resistance issues
Solution Approach 1:
The hardmask structure is divided into multiple segments: first hardmask layer, second hardmask layer, third hardmask layer, and fourth hardmask layer with different materials and functions. Each layer serves specific purposes in the self-aligned via formation process, enabling precise via critical dimension control while managing the complexity through functional segmentation.
Solution Approach 2:
The conductive lines are formed first as preliminary structures, then the self-aligned via formation process uses these pre-formed lines as references. The hardmask layers are deposited and patterned in advance to ensure proper alignment, allowing the via critical dimension to be controlled based on the predetermined conductive line positions.
2Measurement precision
If conventional via alignment is used, then process steps are fewer, but overlay errors increase at small dimensions
Solution Approach 1:
The via formation process is self-aligned, using the previously formed conductive lines and hardmask structures as automatic alignment references. The self-aligned via etch process inherently aligns the via openings with the conductive lines without requiring additional lithographic alignment steps, thereby achieving high overlay precision while maintaining fabrication efficiency.
Solution Approach 2:
The alignment approach transitions from two-dimensional lithographic overlay alignment to three-dimensional self-aligned etching. The via alignment is achieved through vertical etching processes that use the horizontal positions of conductive lines and hardmask layers as automatic references, adding a dimensional aspect that eliminates overlay errors.
3Manufacturing precision
If thick opaque conductive films are used for alignment, then alignment is achieved, but critical dimension variation increases
Solution Approach 1:
Different regions of the structure have different material compositions and properties. The hardmask layers use different materials (first, second, third, and fourth hardmask materials) with varying etch selectivities and properties. This local differentiation allows precise control of via critical dimension in specific regions while managing the overall structure thickness through selective etching processes.
Data Source
AI summary
A method for fabricating a semiconductor device includes recessing a first odd hardmask and a first even hardmask to form recessed odd and even hardmasks, forming a first conductive hardmask including first conductive hardmask material on the recessed odd hardmask and a second conductive hardmask on the recessed even hardmask, and forming self-aligned vias at line ends corresponding to the first odd and even conductive lines based at least in part on the first and second conductive hardmasks.