Self-Aligned Top Via on Etched Conductive Lines
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Solution Overview
Problem
Patterning a via at the top of a conductive line, referred to as a top via, is difficult and can lead to variability in via dimensions and misalignment due to the use of metal reactive-ion etching (RIE) processes, especially when combining conductive line height with via patterning steps.
Innovation Solution
The formation of a damascene via on top of a subtractively etched conductive line, which is self-aligned to the conductive line, is achieved through a process that includes subtractive etching, forming a barrier layer, planarizing, recessing the conductive lines, and filling the via opening with conductive material, eliminating the need for metal RIE and allowing uniform recess without patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal reactive-ion etching (RIE) is used for via patterning, then via formation is achieved, but via dimension variability and misalignment increase
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the conductive line and the via opening. The dielectric layer serves as a protective intermediary that eliminates direct metal etching, thereby preventing etch-induced damage and improving via dimension control. The dielectric material acts as a buffer that maintains alignment accuracy while enabling precise via formation.
Solution Approach 2:
The patent replaces metal reactive-ion etching with dielectric RIE for via patterning. This substitution changes the etching mechanism from metal-based to dielectric-based, eliminating the harmful effects of metal etching while maintaining the precision benefits of RIE. The dielectric etching process provides better via dimension control and reduces misalignment.
2Ease of manufacture
If conductive line height is combined with via patterning steps, then top via formation is achieved, but process complexity and variability increase
Solution Approach 1:
The via formation process is segmented into distinct steps: forming the dielectric layer, patterning the via opening through the dielectric, and filling with conductive material. This segmentation separates the via patterning from conductive line formation, allowing independent optimization of each step and reducing process variability.
Solution Approach 2:
The dielectric layer is formed preliminarily before via patterning. This preliminary action establishes a protective foundation that enables subsequent via formation without directly etching the conductive line, thereby maintaining conductive line height control while enabling top via formation.
3Shape
If subtractive etching is used for conductive line formation, then line geometry is achieved, but etch-induced damage layers are created
Solution Approach 1:
The dielectric layer serves as an intermediary that protects the conductive line from direct etching. By etching the dielectric instead of the metal, the harmful etch-induced damage layers are eliminated while maintaining the desired conductive line geometry.
Solution Approach 2:
The patent converts the potential harm of etching by applying it to the dielectric layer instead of the conductive line. The etching process that would normally damage the metal is redirected to remove only the dielectric material, transforming a harmful process into a beneficial one that preserves conductive line integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method provides better control over conductive line height variability and reduces misalignment by using dielectric RIE, resulting in a lower effective dielectric constant and improved performance due to the absence of etch-induced damage layers.
Implementation Method 1
subtractively etching a conductive layer to form at least a first conductive line on a substrate
Implementation Method 2
forming a barrier layer along the substate and along the first conductive line
Implementation Method 3
planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line
Implementation Method 4
recessing at least the exposed first conductive line to form a first recessed conductive line
Data Source
AI summary
A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.