Self-Aligned Top Via Structure for Low-Resistance BEOL Wiring
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Solution Overview
Problem
Current semiconductor technologies face challenges in forming high-quality vias and interconnects with small dimensions due to misalignment issues, leading to increased electrical resistance and RC delay, particularly in backend of line (BEOL) metal layers, where the placement of vias below trenches makes alignment difficult and causes significant resistance penalties.
Innovation Solution
A self-aligned top via is formed using a method that integrates the top via and line formation within the same metal deposition process, ensuring the top via is directly aligned within the interlayer dielectric trench, reducing misalignment and electrical resistance by matching the diameter of the top via with the underlying metal line, and utilizing a series of dielectric and etch stop layers to control the formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dual damascene process is used to form vias and interconnects, then the via openings and trenches can be formed in a dielectric layer, but misalignment issues occur leading to increased electrical resistance and RC delay
Solution Approach 1:
The patent employs a self-aligned process where the top via is automatically positioned over the metal line through the formation of sidewalls from the metal line itself. The metal line serves as its own alignment reference, eliminating the need for separate alignment steps and ensuring precise positioning that reduces misalignment and electrical resistance.
Solution Approach 2:
The patent performs preliminary recessing of the metal line to create a stepped structure before forming the top via. This preliminary action creates the necessary geometry for self-alignment, where the sidewalls formed during subsequent processing automatically guide the top via placement over the metal line center.
2Manufacturing precision
If traditional via formation methods are used with via openings having tapered edges, then the via can be formed in the dielectric layer, but the smaller cross-sectional area at the bottom increases electrical resistance
Solution Approach 1:
The patent changes the geometric parameters of the via formation process by creating a self-aligned top via with uniform cross-section. Through controlled recessing and sidewall formation, the via maintains a consistent diameter throughout its length, optimizing the cross-sectional area for electrical conduction and reducing resistance.
3Manufacturing precision
If separate processes are used for top via formation and line formation, then each structure can be optimized independently, but additional etch steps and dielectric layer depositions are required
Solution Approach 1:
The patent merges the top via formation and line formation processes into a single integrated sequence. The self-aligned approach allows both structures to be formed simultaneously through coordinated recessing, sidewall formation, and metal deposition steps, eliminating separate etch and deposition processes while maintaining structural optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces electrical resistance and improves the electrical performance of BEOL interconnect wiring by minimizing misalignment and conduction area between the top via and the metal line, while also simplifying the process by eliminating the need for additional etch steps and dielectric layer depositions.
Implementation Method 1
recessing the plurality of metal lines using a wet etching process
Implementation Method 2
depositing a second dielectric material above the plurality of first metal lines
Data Source
AI summary
An approach providing a semiconductor wiring structure with a self-aligned top via on a first metal line and under a second metal line. The semiconductor wiring structure includes a plurality of first metal lines in a bottom portion of a first dielectric material. The semiconductor wiring structure includes a top via in a top portion of the first dielectric material, where the top via is over a first metal line of the plurality of first metal lines. The semiconductor wiring structure includes a second dielectric material above each of the plurality of first metal lines except the first metal line of the plurality of first metal lines. Furthermore, the semiconductor wiring structure includes a second metal line above the top via, wherein the second metal line is in a third dielectric material and a hardmask layer that is under the third dielectric material.