Self-aligned top vias via spacer mandrel patterning
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in achieving precise alignment and consistent formation of self-aligned vias due to reduced pitch between metal lines, leading to misalignment and potential shorts in circuitry, affecting yield, performance, and reliability.
Innovation Solution
The method involves forming elongated dielectric members and spacer walls on a semiconductor substrate, depositing metal materials within trenches to create alternating patterns of metal lines, and using a mandrel cap material to distinguish between odd and even lines, allowing for precise via formation and alignment through selective etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic and etching processes are used to pattern trenches, then metal lines can be formed in the interconnect structure, but via alignment becomes problematic due to reduced pitch between adjacent metal lines, resulting in misalignment and potential shorts
Solution Approach 1:
The patent segments the via formation process into multiple distinct steps: first forming mandrels at initial via locations, then forming spacers around mandrels, selectively removing mandrels, and finally forming vias. This segmentation allows precise control of via positions independent of metal line pitch, resolving the alignment problem caused by reduced pitch.
Solution Approach 2:
The patent performs preliminary actions by forming mandrels at the desired via locations before forming the metal lines. The spacers are then formed around these mandrels, establishing the via positions in advance. This preliminary positioning ensures that subsequent via formation is self-aligned to the metal lines, achieving high precision even with reduced pitch.
2Reliability
If self-aligned via (SAV) approach is used, then via alignment can be maintained, but consistency in producing self-aligned vias is insufficient, leading to shorts and degradations in yield, performance, and reliability
Solution Approach 1:
The patent introduces mandrels as intermediary structures that serve as templates for via formation. These mandrels are formed at precise locations, and spacers are formed around them to define via boundaries. The mandrels act as mediators that transfer the precise positioning information to the final via structures, ensuring consistency and reliability.
Solution Approach 2:
The spacer formation process is self-aligning to the mandrels, automatically defining the via locations without requiring additional alignment steps. The spacers form conformally around the mandrels, and when mandrels are selectively removed, the spacers self-align to the metal lines, ensuring consistent via formation across different structures and improving reliability.
3Manufacturing precision
If mandrels are formed at initial via locations and spacers are formed around mandrels, then precise via alignment can be achieved, but process complexity increases with multiple deposition and etching steps
Solution Approach 1:
The patent merges the via positioning function into the metal line patterning process itself. The spacers that define via locations are formed using the same deposition and etching steps that form the metal lines. This merging reduces process complexity by eliminating separate alignment steps while maintaining high positioning accuracy.
Solution Approach 2:
The spacer formation process is self-aligning to the mandrels and metal lines, automatically defining via locations without requiring additional alignment steps or complex process control. The self-service nature of the spacer formation reduces process complexity while achieving precise via positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor structures with improved via alignment and reduced risk of shorts, enhancing the yield, performance, and reliability of semiconductor devices by maintaining the integrity of previously formed metal lines and vias.
Implementation Method 1
The etching process is selective to the sacrificial dielectric material, allowing removal of the dielectric members without damaging the spacer walls or metal lines
Implementation Method 2
depositing a first metal material within the first trenches to form a first set of first metal lines
Data Source
AI summary
A method includes forming a plurality of elongated dielectric members on a semiconductor substrate. The elongated dielectric members each extend vertically from the semiconductor substrate and define opposed vertical walls. The method further includes forming opposed spacer walls on the vertical walls of the elongated dielectric members. Adjacent spacer walls of longitudinally adjacent elongated dielectric members define first trenches therebetween. The method also includes depositing a first metal material within the first trenches to form a first set of first metal lines, removing the elongated dielectric members to define second trenches between the opposed spacer walls on the opposed vertical walls of each elongated dielectric member, and depositing a second metal material within the second trenches to form a second set of second metal lines. The first and second metal lines of the first and second sets are disposed in alternating arrangement.