Self-Aligned Transistor Contacts via Selective Etch Capping Layers
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Solution Overview
Problem
The miniaturization of semiconductor devices is limited by challenges in forming contacts between semiconductor devices and metallization layers, particularly due to the complexity and defects associated with traditional contact fabrication methods.
Innovation Solution
The use of two selectively etchable capping layers, one for gate coverage and another for source/drain coverage, allows for self-aligned transistor contacts in two dimensions, enabling improved electrical connectivity through a metallization line that intersects with the exposed elements, reducing lithographic requirements and defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional contact fabrication methods are used, then contacts can be formed between semiconductor devices and metallization layers, but the process complexity increases and defects are introduced
Solution Approach 1:
The patent divides the capping layer into two distinct segments: a first capping layer material covering gate contact areas and a second capping layer material covering source/drain contact areas. This segmentation allows selective etching of each layer type, enabling precise contact formation with reduced process complexity and fewer defects compared to using a single uniform capping layer.
Solution Approach 2:
The patent applies different materials (first capping layer material and second capping layer material) to different local regions of the semiconductor structure. The first capping layer material is used where gate contacts are needed, while the second capping layer material is used where source/drain contacts are needed. This local differentiation enables selective removal of capping layers at specific locations, improving contact formation reliability while simplifying the overall process.
2Area of moving object
If device size is reduced for miniaturization, then more devices can be placed on a chip, but contact formation challenges increase and limit further miniaturization
Solution Approach 1:
The patent performs preliminary action by depositing the first and second capping layer materials on the semiconductor structure before contact formation. This pre-established layered capping structure enables subsequent selective etching processes to quickly and accurately form contacts at reduced dimensions without increasing manufacturing difficulty, thus supporting device miniaturization.
Solution Approach 2:
The patent introduces capping layer materials as intermediary layers between the semiconductor device structures and the contact holes. These intermediary capping layers (first and second materials) facilitate controlled selective etching, enabling precise contact formation in miniaturized devices while maintaining ease of manufacture through the mediator's selective removal properties.
3Productivity
If middle-of-line density is increased for better scalability, then more interconnects can be formed, but contact formation becomes more difficult
Solution Approach 1:
The patent segments the capping layer into first and second capping layer materials with different etch selectivities. This segmentation enables independent control of gate contact and source/drain contact formation, allowing high middle-of-line density interconnect formation without proportionally increasing process complexity, as each contact type can be addressed through selective etching of the appropriate capping layer material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances middle-of-line (MOL) density and scalability by simplifying the contact formation process, reducing defects, and improving product yield while maintaining efficient electrical connectivity.
Implementation Method 1
The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains
Implementation Method 2
depositing a metallization layer over the exposed source/drain contact locations and exposed gate contact locations
Implementation Method 3
depositing a metallization layer over the exposed source/drain contact locations and exposed gate contact locations
Data Source
AI summary
Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.