Self-Aligned 3D Semiconductor Transistors with Low-Temperature Ion-Cut Transfer
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Solution Overview
Problem
Current 3D stacked semiconductor chip technologies face challenges in achieving high-density connections between layers due to misalignment issues and the degradation of wiring layers when constructing transistors at high temperatures, leading to limited connectivity and performance bottlenecks.
Innovation Solution
The development of processes that allow for the construction of single-crystal silicon transistors with source-drain regions processed at temperatures below 400°C, using ion-cut layer transfer and junctionless transistors, which enables well-aligned top-level transistors to be formed without damaging underlying wiring layers, and the use of misalignment-tolerant techniques for high-density connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are constructed at high temperatures (higher than 700°C) to achieve standard transistor performance, then transistor functionality is improved, but the underlying wiring layers (constructed at temperatures lower than 400°C) are damaged
Solution Approach 1:
The patent divides the transistor construction process into multiple temperature stages: first forming the transistor structure at low temperature (below 400°C) to protect wiring layers, then performing selective high-temperature processing only on specific regions (source-drain junctions) that require it, rather than heating the entire structure to 700°C
Solution Approach 2:
The patent performs preliminary low-temperature transistor formation before wiring layer construction, establishing the transistor structure in advance at temperatures safe for subsequent wiring processes, thereby preventing wiring damage from high-temperature exposure
2Productivity
If 3D stacking is implemented to reduce wire lengths and improve transistor density, then IC performance is improved, but alignment precision and connectivity between layers deteriorate due to misalignment issues
Solution Approach 1:
The patent replaces mechanical alignment methods with optical alignment techniques, using transparent alignment marks and optical microscopes to achieve sub-micron precision alignment between stacked layers, thereby improving alignment precision while maintaining high transistor density
Solution Approach 2:
The patent changes the alignment precision parameter by introducing specialized alignment marks with high contrast and visibility, and by optimizing the alignment process parameters (such as microscope magnification and mark design) to achieve better than 1-micron alignment accuracy between layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of 3D stacked semiconductor chips with increased connectivity and performance by maintaining the integrity of wiring layers and allowing for high-density inter-layer connections, overcoming the limitations of existing technologies.
Implementation Method 1
using ion-cut layer transfer
Implementation Method 2
these two wafers are bonded to each other
Data Source
AI summary
A device, including: a first layer including first transistors and a second layer including second transistors, where at least one of the first transistors is self-aligned to one of the second transistors, where the second transistors are horizontally oriented transistors, and where the second layer includes a plurality of resistive-random-access memory (RRAM) cells, the memory cells including the second transistors.