Self-Aligned Vertical Transistor Structure for Ultra-Low OFF Leakage
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Solution Overview
Problem
Conventional transistors, especially fin-structure transistors, face high leakage currents during the OFF state, which is problematic for deep nanometer silicon technology, particularly in memory circuits like SRAM and DRAM, as they require low leakage currents to maintain signal integrity, but scaling down transistor dimensions to achieve this is impractical due to increased gate length and other leakage mechanisms.
Innovation Solution
A new transistor design with self-aligned, vertically structured source and drain regions and a gate structure that allows for a compact form factor and adjustable ON/OFF current capabilities, utilizing spacers and insulators to reduce leakage currents and enable scaling down of transistor size, including a short gate length, while maintaining low leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to reduce cell size, then productivity and Moore's Law economy are improved, but OFF state leakage current increases making the device unreliable
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional FinFET structures with vertical channel regions. This dimensional change allows the channel to extend vertically into the substrate, providing better gate control over the current flow path while maintaining a compact planar footprint, thus reducing leakage current without sacrificing scaling benefits
Solution Approach 2:
The patent implements nested structures where the gate electrode wraps around the vertical channel region in a FinFET configuration, and further nesting occurs with multiple fins arranged in parallel within a single transistor device. This nested architecture maximizes the effective channel area within a small planar footprint, achieving low leakage current while maintaining scalability
2Reliability
If gate length is increased to reduce OFF current, then leakage current is reduced, but transistor size increases violating scaling requirements
Solution Approach 1:
The patent extends the channel region vertically into the substrate to form fins, allowing the effective channel length to be achieved through vertical depth rather than horizontal extension. This enables sufficient channel length for low leakage while maintaining short gate lengths for scaling, as the gate controls current through the vertical fin structure rather than requiring long horizontal channels
Solution Approach 2:
The patent changes the geometric parameters of the transistor structure by creating high aspect ratio vertical fins with controlled depths and widths. By adjusting the fin height, width, and spacing parameters, the device achieves the necessary effective channel length for low leakage current while keeping the planar gate length short to satisfy scaling requirements
3Power
If fin-structure transistors are used to improve current drive capability, then ON current is improved, but OFF state leakage current increases
Solution Approach 1:
The patent applies different doping concentrations to different regions of the fin structure, with heavily doped source/drain regions for low resistance contacts and lightly doped channel regions for high control. This local quality variation allows the fin structure to provide high ON current through optimized source/drain regions while maintaining low OFF current through controlled channel doping, resolving the contradiction between drive capability and leakage reduction
Data Source
AI summary
A transistor structure includes a gate structure, a channel region, a drain region and a source region. The gate structure is positioned above a silicon surface of a first silicon material, the channel region is under the silicon surface, and the channel region includes a first terminal and a second terminal. The drain/source region is independent and not derived from the first silicon material, the drain region includes a first predetermined physical boundary directly connected to the first terminal of the channel region, and the source region includes a second predetermined physical boundary directly connected to the second terminal of the channel region. The drain/source region includes a lower portion below the silicon surface and the bottom of the lower portion of the drain/source region is confined to an isolator, and sidewalls of the drain/source region are confined to spacers except sidewalls of the lower portion of the drain/source region.