Self-Aligned Transistor Contacts via Spacer Formation
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Solution Overview
Problem
Conventional methods for manufacturing transistor devices face challenges in miniaturization and cost reduction due to alignment tolerances and high costs associated with photolithographic masks, particularly in ensuring adequate contact spacing to avoid increased resistance and yield fallout.
Innovation Solution
A method involving a gate structure over a substrate with an insulating layer, where openings are formed to the substrate and filled with conducting material to form interconnects, allowing for self-aligned contacts to the gate, thereby reducing the need for precise alignment and minimizing the cost of photolithographic masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic alignment methods are used to position contacts relative to the gate, then alignment precision can be maintained within tolerance ranges, but device density decreases due to required spacing between contacts and sidewall spacers
Solution Approach 1:
The contact openings are self-aligned to the gate structure through the spacer formation process. The spacer automatically defines the contact position relative to the gate, eliminating the need for separate photolithographic alignment steps and reducing the required spacing between contacts and spacers.
Solution Approach 2:
The sidewall spacer is formed in advance before contact opening formation. This preliminary spacer formation establishes the contact position boundaries beforehand, ensuring proper alignment without requiring precise photolithographic alignment during the contact opening step.
2Manufacturing precision
If multiple photolithographic masks are used for pattern alignment, then manufacturing precision is maintained, but manufacturing cost increases significantly
Solution Approach 1:
The spacer structure serves as a self-aligning reference for contact opening formation. The contact openings are defined by the spacer geometry rather than by photolithographic masking, eliminating the need for expensive minimum-geometry masks and reducing manufacturing costs.
Solution Approach 2:
The alignment function is extracted from the photolithographic masking process and transferred to the spacer structure. The spacer becomes the alignment reference, removing the requirement for separate alignment masks and reducing the number of photolithography steps.
3Productivity
If contact openings are formed with minimum spacing to sidewall spacers, then device density increases, but contact resistance increases and yield decreases due to alignment tolerance violations
Solution Approach 1:
The spacer automatically defines the minimum safe distance between the contact opening and the gate structure. This self-aligned approach ensures that contacts never violate the critical spacing to the gate, eliminating yield losses from alignment errors while maximizing device density.
Solution Approach 2:
The spacer structure provides a built-in safety margin or 'cushion' between the contact opening and the gate. This pre-established buffer zone protects against alignment variations and ensures adequate spacing is maintained even under maximum misalignment conditions, preventing contact resistance increases and yield fallout.
Data Source
AI summary
The present invention provides a method of manufacturing a transistor device, a transistor device, and a method for manufacturing an integrated circuit. In one aspect, the method of manufacturing a transistor device includes providing a gate structure (140) over a substrate (110). An insulating layer (310) is formed over the gate structure (140), and openings (710) to the substrate (110) are formed therein, thereby removing a portion of the gate structure (140). The openings (710) are filled with a conductor (1410), thereby forming an interconnect (1510).