Partially Self-Aligned Trench Formation via Selective Etch Layers
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Solution Overview
Problem
Conventional lithography techniques face challenges in forming small trench dimensions due to high costs and poor critical dimension uniformity, especially when blocking patterns are misaligned, leading to issues like gate shorting in advanced IC fabrication.
Innovation Solution
A semiconductor device fabrication method involving a semiconductor substrate with gate structures, sidewall spacers, an etch stop layer, interlayer dielectric layers, and an etch buffer layer, which allows for partially self-aligned trench formation using different etch rates and selective etching to achieve smaller trench dimensions without misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography is used to form small trench dimensions, then high cost exposure tools are required, but manufacturing precision deteriorates due to poor critical dimension uniformity and gate shorting
Solution Approach 1:
The patent divides the trench formation process into multiple stages using different etch selectivity layers (first etch selectivity layer with higher selectivity, second etch selectivity layer with lower selectivity). This segmentation allows each layer to be optimized for specific etching requirements, enabling precise trench formation without requiring advanced lithography tools, thus resolving the contradiction between manufacturing precision and ease of manufacture
Solution Approach 2:
The patent applies preliminary patterning actions to form the etch selectivity layers before the final trench etching. The first etch selectivity layer is formed with a pattern that anticipates the final trench geometry, and subsequent etching steps refine this pattern. This preliminary action enables precise dimension control using conventional lithography, avoiding the need for expensive EUV tools while maintaining high manufacturing precision
2Manufacturing precision
If a large etching bias is used to compensate for lithographic pattern limitations, then non-shrinkable critical dimensions are maintained, but critical dimension uniformity deteriorates and gate shorting occurs
Solution Approach 1:
The patent applies different etch selectivity characteristics to different regions and layers: the first etch selectivity layer has higher selectivity for controlling trench width, while the second etch selectivity layer has lower selectivity for other functions. This local differentiation of etch properties enables precise critical dimension control without excessive etch bias, maintaining both critical dimension uniformity and gate integrity
Solution Approach 2:
The patent changes the etch selectivity parameter between different layers to achieve precise trench formation. By using a first etch selectivity layer with higher selectivity ratio and a second etch selectivity layer with lower selectivity ratio, the process achieves accurate dimension control with reduced etch bias, preventing gate shorting while maintaining critical dimension uniformity
Data Source
AI summary
A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, an etch stop layer disposed over the sidewall spacers, an interlayer dielectric (ILD) layer disposed on a bottom portion of the etch stop layer, an etch buffer layer disposed on an upper portion of the etch stop layer, and a plurality of metal plugs between the gate structures. An upper portion of the metal plugs is adjacent to the etch buffer layer and a lower portion of the metal plugs is adjacent to the ILD layer.