Self-Aligned Nanometer TSV Structure for Low-Resistance BPR Contact
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Solution Overview
Problem
Current Backside Power Delivery Network technology is limited by high interface contact resistance between Buried Power Rail and Nanometer Through-Silicon-Via, and lithography alignment issues, hindering the miniaturization of MOSFET devices.
Innovation Solution
A self-aligned nanometer through-silicon-via structure is developed using a method that involves sequential etching and filling processes, including the growth of SiO2 layers and sacrificial layers, to form trenches and blind holes, with tungsten and copper fillers, and the application of electrical isolation and diffusion barrier layers, which reduces interface contact resistance and aligns buried power rails with nanometer through-silicon-vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography alignment methods are used for N-TSV formation, then existing process compatibility is maintained, but lithography alignment problems occur between buried power rail and nanometer through-silicon-via
Solution Approach 1:
The patent applies preliminary action by forming the buried power rail structure before the N-TSV structure using sequential etching processes. The first etching process creates the buried power rail at a predetermined depth, and the second etching process subsequently forms the N-TSV. This predetermined sequence ensures automatic alignment between the two structures, eliminating lithography alignment problems while maintaining process compatibility.
2Reliability
If standard etching processes are used for BPR and N-TSV formation, then process simplicity is maintained, but high interface contact resistance occurs between BPR and N-TSV
Solution Approach 1:
The patent applies segmentation by dividing the etching process into two distinct sequential processes: a first etching process for forming the buried power rail and a second etching process for forming the N-TSV. This segmentation allows independent optimization of each etching process parameters, enabling precise control over the interface between BPR and N-TSV, thereby reducing interface contact resistance while managing process complexity.
Solution Approach 2:
The patent applies parameter changes by adjusting etching depth parameters to achieve precise positioning. The first etching process etches to a first predetermined depth to form the BPR, and the second etching process etches to a second predetermined depth to form the N-TSV. By controlling these depth parameters, the interface between BPR and N-TSV is optimized for low contact resistance.
3Reliability
If deeper etching is used to improve contact area, then interface contact resistance decreases, but manufacturing precision and alignment control become more difficult
Solution Approach 1:
The patent applies preliminary action by establishing the buried power rail structure at a first predetermined depth before forming the N-TSV. This predetermined depth serves as a reference that automatically guides the subsequent N-TSV formation, ensuring proper alignment and contact area without requiring complex real-time depth control during the second etching process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces interface contact resistance and addresses lithography alignment problems, enabling further miniaturization of finned field-effect transistor devices and facilitating the widespread application of backside power delivery network technology.
Implementation Method 1
An anisotropic etching selective ratio of a material used in the sacrificial layer to the silicon substrate, the first SiO2 layer, the first filler, and the second filler are less than or equal to a preset ratio, and the preset ratio is 1:10
Implementation Method 2
sequentially growing an electrical isolation layer, a diffusion barrier layer, and an adhesive layer at a bottom and a side wall of the target trench and the first target blind hole
Data Source
AI summary
Provided are a self-aligned nanometer through-silicon-via structure and a method of preparing the same. According to the preset range and positions of the first and second trenches, the second preset pattern is formed, and then the first initial blind hole is formed by etching based on the second preset pattern, so that the position of the nanometer through-silicon-via is determined. The depth of the buried power rail may be determined by etching the silicon substrate with the first preset depth, and the depth of the self-aligned nanometer through-silicon-via may be determined by etching the silicon substrate with the second preset depth or thinning the fourth structure from a side of the silicon substrate.