Self-Aligned TSV Formation for Buried Interconnect Rail Contact
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Solution Overview
Problem
The increasing device density in integrated circuit chips poses challenges for the integration of power delivery networks in the back end of line, particularly due to wafer distortion and alignment issues with buried interconnect rails, limiting scalability to smaller dimensions.
Innovation Solution
The method involves forming Through Semiconductor Vias (TSVs) in a self-aligned manner during the front end of line process, allowing them to be connected to buried interconnect rails on the backside of the chip, enabling precise alignment and scaling down to smaller dimensions without losing positioning accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If TSVs are etched from the back side after wafer bonding, then the PDN can be formed on the backside of the IC, but wafer distortion and non-linear pattern deformation occur, causing misalignment between TSVs and buried interconnect rails
Solution Approach 1:
The TSVs are formed during the FEOL process before wafer bonding, ensuring their positions are predetermined and self-aligned to the buried interconnect rails. This preliminary formation of TSVs prevents alignment issues that would otherwise occur due to wafer distortion during bonding, as the TSV positions are locked in before the bonding-induced deformation occurs.
2Quantity of substance
If device density is increased, then more active devices can be placed on the chip, but the integration of power delivery network becomes more challenging due to scaling limitations
Solution Approach 1:
The power delivery network is moved from the traditional front-side implementation to the backside of the IC. This dimensional relocation allows the PDN to be integrated independently of the front-end device scaling, enabling the PDN to accommodate higher device densities without being constrained by the same scaling limitations that affect front-side interconnects.
Data Source
Figure 1a~1b
Figure 1c~1d
Figure 1e
AI summary
The invention is related to a method for producing an integrated circuit chip on a semiconductor device wafer, the IC comprising buried interconnect rails (15) in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized Through Semiconductor Via (TSV) connections (16) through the thinned semiconductor wafer. Contrary to existing methods, the production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.