Self-Aligned Via Formation Using Conformal Etch Protection
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Solution Overview
Problem
The production of via connections in nano-scaled transistors faces challenges due to limitations in standard lithography processes, particularly in controlling overlay between layers, leading to inaccuracies and incompatibility issues with mask materials during self-aligned contact etch steps.
Innovation Solution
A method involving two separate self-aligned etch processes, Vint-A and Vint-G etches, where a conformal layer resistant to the second etch process is deposited after the first etch, protecting the initial contact via and allowing for carbon-free etching environments, thereby overcoming material compatibility and micro-loading effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate self-aligned patterning steps are used for producing Vint-G and Vint-A vias, then overlay-related inaccuracies are avoided, but the first via exposes materials that are attacked during the second etch step
Solution Approach 1:
A conformal protective layer is deposited over the first via structure before performing the second etch step. This preliminary protective action prevents the exposure and damage of previously formed via materials during subsequent processing, while maintaining the self-aligned precision achieved in the first step.
Solution Approach 2:
The conformal protective layer acts as an intermediary barrier between the first via structure and the second etch process. This intermediate layer protects sensitive materials from direct exposure to harmful etchants while allowing the second etch to proceed for forming the gate via.
2Ease of manufacture
If SOC hardmask is used for self-aligned patterning, then via formation is enabled, but it is incompatible with carbon-free etch recipes required for selective silicon oxide removal
Solution Approach 1:
The patent changes the material parameter of the protective layer from carbon-based (SOC hardmask) to carbon-free conformal material. This parameter change enables compatibility with carbon-free etch recipes while maintaining the necessary protective function and self-aligned patterning capability.
Solution Approach 2:
The solution uses a composite approach by combining conformal deposition technology with selective etch processes. The conformal protective layer material is specifically chosen to be compatible with both the patterning requirements and the carbon-free etch chemistry, creating a multi-functional material system.
3Reliability
If additional SOC hardmask is deposited and etched back to form protective plugs, then via protection is achieved, but micro-loading effects occur and etch-back uniformity is insufficient
Solution Approach 1:
The patent extracts the problematic etch-back step from the process flow by using a conformal protective layer that does not require removal. This eliminates the micro-loading effects and uniformity issues associated with etch-back, while maintaining via protection through the conformal layer's inherent resistance to the second etch process.
Solution Approach 2:
Instead of using a disposable SOC hardmask that requires etch-back removal, the patent employs a conformal protective layer that serves its protective function and can be selectively removed or retained based on process requirements, avoiding the complications of etch-back uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures precise and accurate formation of self-aligned via connections between gate and source/drain electrodes, improving etch uniformity and reducing overlay-related inaccuracies, enabling reliable contact formation at nano-sized dimensions.
Implementation Method 1
a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process
Implementation Method 2
selective plasma etch steps are applied to locally remove dielectric plugs from the top of the gate and S/D electrodes
Data Source
AI summary
The disclosed technology is related to a method that includes the formation of contact vias for contacting gate electrodes and source (S) or drain (D) electrodes of nano-sized semiconductor transistors formed on a semiconductor wafer. The electrodes are mutually parallel and provided with dielectric gate and S/D plugs on top of the electrodes, and the mutually parallel electrode/plug assemblies are separated by dielectric spacers. The formation of the vias takes place by two separate self-aligned etch processes, the Vint-A etch for forming one or more vias towards one or more S/D electrodes and the Vint-G etch for forming one or more vias towards one or more gate electrodes. According to the disclosed technology, a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process. The conformal layer thereby protects the first contact via during the second self-aligned etch.