Self-Aligned Via Structure for Low-Resistance FinFET Contacts
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Solution Overview
Problem
Existing FinFET manufacturing processes face challenges in forming reliable via and contact structures at smaller sizes, which affect device performance and reliability.
Innovation Solution
A method is introduced for forming a semiconductor device structure with a self-aligned contact structure and via structures that are electrically connected to a gate stack without recessing the contact structure, simplifying the manufacturing process and reducing resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device scaling-down continues to increase device density, then higher device density is achieved, but forming reliable via and contact structures becomes more challenging
Solution Approach 1:
The method performs preliminary actions by forming a capping layer over the contact structure before forming the via structure. This preliminary capping layer formation enables subsequent via formation processes to proceed without compromising the contact structure, even at scaled dimensions. The capping layer is formed in advance to protect and define the contact structure geometry during subsequent processing steps.
Solution Approach 2:
The manufacturing process is segmented into distinct sequential steps: forming the contact structure, forming the capping layer over the contact structure, and then forming the via structure. This segmentation allows each structure to be formed and stabilized independently, ensuring reliability of both contact and via structures even as device dimensions scale down.
2Quantity of substance
If via and contact structures are formed at smaller sizes, then device density increases, but manufacturing complexity increases
Solution Approach 1:
The method merges the contact structure and via structure formation into an integrated self-aligned process. The capping layer formed over the contact structure serves dual purposes: it protects the contact structure and simultaneously defines the alignment for the subsequent via structure formation. This merging reduces the need for separate alignment and positioning steps that would otherwise increase manufacturing complexity.
Solution Approach 2:
The capping layer formed over the contact structure serves as a self-aligned mask and definition layer for the via structure formation. The via structure automatically aligns to the contact structure through this self-service mechanism, eliminating the need for additional alignment procedures and reducing manufacturing complexity while enabling continued device scaling.
3Ease of manufacture
If via structures are formed without recessing the contact structure, then manufacturing process is simplified, but contact resistance may increase
Solution Approach 1:
The capping layer is formed in advance over the contact structure before via formation. This preliminary action creates a protective and conductive interface that maintains low contact resistance during the subsequent via formation process, even when the via is formed without recessing the contact structure.
Solution Approach 2:
The structure employs composite material layers including the capping layer formed over the contact structure. This composite construction combines materials with different properties to simultaneously achieve ease of manufacture (through simplified via formation) and low contact resistance (through the specialized capping layer material and structure).
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer and first and second gate spacers in first and second openings of the first insulating layer, respectively, forming a first conductive gate stack adjacent to the first gate spacer and forming an insulating material adjacent to the second gate spacer after forming the first conductive gate stack. The method also includes covering the first conductive gate stack and the insulating material with a first insulating capping layer and a second insulating capping layer, respectively, and forming a source/drain contact structure between the first and second gate spacer layers. The top surface of the first insulating layer is higher than those of the insulating material and is substantially level with that of the first conductive gate stack.