Self-Aligned Via Etching with High Corner Selectivity
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Solution Overview
Problem
As semiconductor device sizes shrink, the metallization of self-aligned via features becomes increasingly problematic, leading to defects during the etching process in multi-layered dielectric stacks.
Innovation Solution
A method involving mixed mode pulsed etching is used to etch self-aligned contact/via features in a low-k dielectric layer, with cycles comprising thinning the planarization layer, forming a deposition layer, and etching the low-k dielectric layer masked by the deposition layer, while maintaining high corner selectivity and minimizing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device sizes are shrunk to enable scaling, then productivity and device density are improved, but metallization of self-aligned via features becomes problematic and defects increase
Solution Approach 1:
The patent applies periodic action by using mixed mode pulsed etching with alternating high-power and low-power phases. The high-power phase removes material while the low-power phase allows polymer deposition to protect corners, creating a periodic cycle that maintains corner selectivity during deep via etching at scaled dimensions
Solution Approach 2:
The patent changes etching parameters by adjusting RF power between high and low states, modifying gas flow ratios (CF4/N2), and controlling deposition thickness dynamically during the etch process to maintain corner protection while achieving the required etch depth for scaled devices
2Ease of manufacture
If conventional etching is used to etch self-aligned vias, then process simplicity is maintained, but corner selectivity is poor and defects increase
Solution Approach 1:
The mixed mode pulsed etching process uses periodic alternation between high-power etching phases and low-power deposition phases, creating cycles that deposit polymer material on vertical sidewalls and corners while removing material from horizontal surfaces, thereby achieving high corner selectivity
Solution Approach 2:
The patent introduces a polymer deposition layer as an intermediary that selectively deposits on vertical surfaces and corners during low-power phases, acting as a protective mask that preserves corner geometry while allowing etching to proceed in other regions
3Reliability
If aspect ratio is reduced to improve metallization, then via depth is decreased, but etching selectivity and process control become more challenging
Solution Approach 1:
The periodic mixed mode pulsed etching creates alternating phases where high-power removes material and low-power deposits protective polymer, maintaining consistent corner protection throughout the via depth and enabling precise control of etching selectivity even in high aspect ratio structures
Solution Approach 2:
The process incorporates feedback by monitoring etch rate, deposition thickness, and corner morphology in real-time, dynamically adjusting RF power, gas flow, and cycle timing to maintain optimal corner selectivity and etching control throughout the via formation process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves high corner selectivity and reduces defects, allowing for reliable metallization and defect-free contacts in the <10 nm technology node, with improved metal hardmask corner selectivity and reduced aspect ratio, enabling efficient etching of self-aligned vias and trenches.
Implementation Method 1
forming a deposition layer on the hardmask and planarization layer
Implementation Method 2
etching the low-k dielectric layer masked by the deposition layer
Data Source
AI summary
A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarization layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low-k dielectric layer masked by the deposition layer.