Self-Aligned Via Fabrication via Double-Trench Constrained Etching
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Solution Overview
Problem
As semiconductor devices miniaturize, the challenge of fabricating properly aligned vias increases, as misaligned vias can cause shorts or voltage breakdowns due to decreased tolerances for misalignment.
Innovation Solution
A self-aligned via is fabricated using a double-trench constrained self-alignment process, where a first dielectric layer is etched to create a trench, filled with metal, and then a second trench is formed with different etching sensitivities to ensure precise alignment and electrical coupling of conductive paths across layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via fabrication methods are used, then the fabrication process is simpler, but alignment precision deteriorates leading to misaligned vias
Solution Approach 1:
The method performs preliminary actions by forming mandrels and dielectric layers in specific sequences before via formation. The first dielectric layer is deposited and patterned to define mandrels, followed by metal filling, then a second dielectric layer is deposited. This preliminary structuring creates self-alignment constraints that guide subsequent via formation, ensuring precise alignment without requiring complex real-time alignment procedures.
Solution Approach 2:
The fabrication method employs self-aligned via formation where the via alignment is automatically determined by the previously formed mandrels and dielectric layer structures. The selective etching of the second dielectric layer exposes metal portions based on the mandrel geometry, creating self-aligned via openings without requiring additional alignment steps. The structure serves itself to define the via positions, eliminating the need for separate alignment procedures.
2Volume of moving object
If device miniaturization is pursued, then device size decreases, but via alignment tolerance decreases leading to increased misalignment risk
Solution Approach 1:
The dielectric structure is segmented into multiple layers with different etching sensitivities. The first dielectric layer contains mandrels that define horizontal conductive paths, while the second dielectric layer is selectively removed to expose vertical metal portions for via formation. This segmentation allows each layer to serve a specific function in the alignment process, with the mandrels acting as alignment references that constrain via positioning even in miniaturized devices.
Solution Approach 2:
Different regions of the dielectric structure have different etching sensitivities. The second dielectric layer is formulated to be selectively etched relative to the first dielectric layer, allowing localized removal of material to expose specific metal portions while leaving other regions intact. This local quality difference enables precise via formation at specific locations determined by the mandrel geometry, maintaining alignment precision in miniaturized devices.
Data Source
AI summary
A self aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method includes forming a first trench and depositing a first metal into the first trench. Afterwards, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as the top surface of the first trench. Next, a second trench is formed and a via is formed by etching the portion of the dielectric layer exposed by the overlapping region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited into the second trench such that the second metal is electrically coupled to the first metal.