Self-Aligned Via Structure Using a Non-Planar Etch Stop Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink in size, maintaining precise alignment between features becomes increasingly difficult due to overlay shifts in photolithography and etching processes, leading to issues like increased leakage current and electrical shorts.
Innovation Solution
The formation of a non-planar etch stop layer (ESL) with a first lower surface contacting the conductive line and a second lower surface spaced apart from it, allowing for self-aligned via formation by recessing the conductive lines and using a non-planar ESL to maintain a minimum distance from adjacent lines, reducing misalignment effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but alignment precision between features deteriorates due to overlay shifts
Solution Approach 1:
The method performs preliminary recessing of conductive lines and selective removal of the etch stop layer before via formation. By pre-positioning the conductive lines at a lower level and creating a non-planar etch stop layer with different lower surfaces, the structure is prepared in advance to accommodate overlay shifts, ensuring that vias will be self-aligned to the conductive lines regardless of photolithography alignment variations.
Solution Approach 2:
The etch stop layer is configured to enable self-aligned via formation. The non-planar etch stop layer, with its first lower surface contacting the conductive line and second lower surface spaced apart, allows the via etch process to automatically align to the conductive line position through the etch stop layer's geometry, eliminating the need for precise photolithography alignment and making the process self-correcting.
2Ease of manufacture
If conventional planar etch stop layer is used, then manufacturing process is simple, but overlay shifts cause increased leakage current and electrical shorts
Solution Approach 1:
The etch stop layer is given non-planar geometry with different local properties: the first lower surface contacts the conductive line while the second lower surface is spaced apart from adjacent conductive lines. This local differentiation in the etch stop layer structure provides different functions in different regions - enabling via formation at the correct location while maintaining isolation from adjacent lines, thus reducing leakage current and preventing shorts.
3Device complexity
If conventional via formation method is used, then manufacturing steps are fewer, but misalignment between vias and conductive lines increases
Solution Approach 1:
The etch stop layer is configured to enable self-aligned via formation. The non-planar etch stop layer, with its first lower surface contacting the conductive line and second lower surface spaced apart, allows the via etch process to automatically align to the conductive line position through the etch stop layer's geometry, eliminating the need for precise photolithography alignment and making the process self-correcting.
Data Source
AI summary
A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.