Self-Aligned Via Etching for Semiconductor Contact Regions
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Solution Overview
Problem
Conventional etch processes, such as reactive ion etching, face challenges in maintaining selectivity and accuracy when dealing with intricate critical dimensions in semiconductor devices, leading to edge-placement errors and over-etching issues, which are exacerbated by the increasing aspect ratios and shrinking transistor structures.
Innovation Solution
The proposed method involves a self-aligned patterning process using a dry etch with a plasma-enhanced fluorine-containing precursor, which selectively recesses metal layers and forms dielectric materials with specific etch chemistries to ensure complete access to underlying metal recesses, reducing the number of material layers and queue times, and improving structural formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional reactive ion etching is used, then etching capability is achieved, but selectivity and accuracy deteriorate leading to edge-placement errors and over-etching
Solution Approach 1:
The etch process is divided into multiple selective removal operations with different chemistries. The first operation uses chemistry selective to the third dielectric material, and the second operation uses chemistry selective to both third and second dielectric materials. This segmentation allows precise control over which materials are removed at each stage, preventing over-etching and improving edge-placement accuracy.
Solution Approach 2:
The patent changes the chemical parameters of the etch process by using fluorine-containing precursors with specific selectivities. By adjusting the chemistry parameters to achieve greater selectivity toward the second dielectric material compared to the third, the process maintains accurate etch profiles while preventing harmful over-etching effects.
2Manufacturing precision
If standard etch selectivities are used, then general etching is achieved, but precision deteriorates at current and future device scales
Solution Approach 1:
The patent forms a liner layer over the recessed metal before forming the second dielectric material. This preliminary action creates a protective barrier that enables subsequent selective removal operations to precisely expose the metal contact region without damaging surrounding structures, achieving high precision at nanometer-scale device dimensions.
Solution Approach 2:
The second dielectric material acts as an intermediary layer that is selectively removed to expose the metal contact region. This intermediary approach allows controlled access to the underlying metal while protecting other structures, maintaining precision in material removal at scaled device dimensions.
3Manufacturing precision
If wet HF etching is used, then silicon oxide removal is achieved, but penetration into constrained trenches deteriorates and material deformation occurs
Solution Approach 1:
The patent replaces wet chemical etching with a dry etch process using plasma-enhanced fluorine-containing precursors. This substitution eliminates the deformation and penetration issues associated with wet etching while maintaining high selectivity through chemical control, enabling effective etching of constrained trench structures.
4Ease of operation
If dry etching is used, then trench penetration is improved, but top-to-bottom profile control deteriorates
Solution Approach 1:
The dry etch process is segmented into two selective removal operations with different chemistries. The first operation targets the third dielectric material, and the second operation targets both third and second dielectric materials. This segmentation maintains good trench penetration while improving profile control through selective material removal at each stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the exposure of contact regions, reduces edge-placement errors, and maintains precise control over etch profiles, thereby improving the quality and accuracy of semiconductor structures by providing greater selectivity and minimizing the inclusion of additional patterning operations or liner materials.
Implementation Method 1
at least one of the first selective removal operation and the second selective removal operation may include a dry etch using a plasma enhanced fluorine-containing precursor
Implementation Method 2
Chemical etching is used for a variety of purposes including transferring a pattern in photoresist into underlying layers, thinning layers, or thinning lateral dimensions of features already present on the surface
Data Source
AI summary
Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively recessing a first metal on a semiconductor substrate with respect to an exposed first dielectric material. The methods may include forming a liner over the recessed first metal and the exposed first dielectric material. The methods may include forming a second dielectric material over the liner. The methods may include forming a hard mask over selected regions of the second dielectric material. The methods may also include selectively removing the second dielectric material to expose a portion of the liner overlying the recessed first metal.