Self-Aligned Via Structure for Compact Phase-Change Memory Heating
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Solution Overview
Problem
Traditional photoresist approaches for via patterning in semiconductor manufacturing face limitations due to resolution constraints and issues like photoresist scum and poor critical dimension uniformity, which hinder the formation of compact and efficient heating elements for phase-change memory cells.
Innovation Solution
A method involving the formation of bottom vias with a low width-to-height ratio using a sacrificial layer and hard mask layer process, allowing for self-aligned via hole creation without photolithographic patterning, and filling these vias with conductive materials like titanium nitride to enhance heating efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photoresist approach is used for via patterning, then the process is simple and familiar, but resolution is limited and critical dimension uniformity is poor
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary component that enables precise via patterning. This sacrificial layer is deposited over the substrate and patterned to define via locations, serving as a mediator between the photoresist patterning step and the actual via formation. The sacrificial layer allows for better critical dimension control while maintaining process simplicity.
Solution Approach 2:
The patent applies preliminary action by depositing and patterning the sacrificial layer before forming the vias. This preliminary structuring step establishes precise via locations and dimensions in advance, enabling subsequent via formation processes to achieve high critical dimension uniformity without requiring complex photoresist formulations or multiple patterning steps.
2Power
If via size is reduced to improve heating efficiency, then heating efficiency increases, but photoresist resolution limitations prevent further scaling
Solution Approach 1:
The sacrificial layer acts as an intermediary that decouples the via dimension control from photoresist resolution limits. By using the sacrificial layer to define via dimensions through deposition control rather than photoresist patterning, the method enables smaller via sizes with better dimensional control, directly improving heating efficiency while overcoming photoresist resolution barriers.
Solution Approach 2:
The patent replaces the optical/mechanical photoresist patterning system with a deposition-based sacrificial layer system. This substitution allows via dimensions to be controlled by thin film deposition processes rather than optical resolution, enabling precise control of smaller via features that improve heating efficiency without being constrained by photoresist capabilities.
3Volume of moving object
If compact heating element is formed to reduce form factor, then device size decreases, but photoresist scum issues arise
Solution Approach 1:
The sacrificial layer serves as an intermediary that eliminates photoresist scum issues by replacing photoresist-based patterning with sacrificial layer deposition and patterning. This intermediary approach allows compact via formation without the adhesion and scum problems associated with photoresist, enabling smaller device form factors with clean interfaces.
Solution Approach 2:
The patent extracts the photoresist material from the via patterning process and replaces it with a sacrificial layer approach. This extraction removes the source of photoresist scum problems while maintaining the ability to form compact vias, thereby reducing device form factor without introducing harmful photoresist residues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of vias with high resistivity, improving the writing speed of phase-change memory cells by achieving high heating efficiency and integrating seamlessly into existing semiconductor manufacturing processes.
Implementation Method 1
A compact heating element, such as a via made by titanium nitride (TiN) in physical contact with the phase-change material in some embodiments, helps to reduce phase-change memory's form factor due to its smaller size, and also increases phase-change memory's speed due to its higher heating efficiency.
Data Source
AI summary
A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.