Self-Aligned Via Formation for IC Interconnects
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Solution Overview
Problem
Conventional via manufacturing techniques in integrated circuit (IC) production lead to misalignment, increased via resistance, and damage to dielectric materials, resulting in device failures, reduced yield, and increased manufacturing costs.
Innovation Solution
A method for creating fully self-aligned vias by depositing conductive lines in trenches, forming pillars, and selectively etching insulating layers to achieve vias with a tapering angle between 60° to 120°, reducing via resistance and minimizing damage to dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via manufacturing techniques are used, then via formation is achieved, but via misalignment occurs leading to increased via resistance and potential shorting
Solution Approach 1:
The method performs preliminary patterning of the first conductive lines and recessing them below the capping layer surface before via formation. This preliminary action establishes precise alignment references that guide subsequent via drilling, ensuring vias are automatically aligned to the conductive lines without requiring separate alignment steps, thereby reducing via resistance and preventing shorting
Solution Approach 2:
The via formation process uses the previously formed conductive lines and capping layer structure as self-aligning references. The via drilling process automatically aligns to these pre-formed features through the self-aligned via technique, eliminating the need for external alignment systems and reducing misalignment errors that would increase via resistance
2Length of moving object
If high aspect ratio etch is used for via formation, then via depth is achieved, but dielectric material damage occurs and performance is limited
Solution Approach 1:
The method performs preliminary recessing of the first conductive lines below the capping layer surface before via formation. This preliminary action reduces the effective via depth that requires high-energy etching, allowing shallower via drilling that causes minimal damage to surrounding dielectric materials while still achieving the required electrical connection depth
Solution Approach 2:
The method changes the via geometry parameters by creating tapered vias with controlled angles (60°-120°) and adjusting via diameter ratios. These parameter changes optimize the via profile to reduce stress concentration and minimize damage to dielectric materials during and after via formation, while maintaining adequate electrical connection
3Reliability
If via resistance is reduced by controlling via material resistivity, then electrical performance is improved, but manufacturing complexity increases
Solution Approach 1:
The method performs preliminary formation of conductive lines and selective recessing before via filling. This preliminary action creates optimized via geometries with larger cross-sectional areas and tapered profiles that naturally reduce via resistance. By addressing resistance through geometric optimization rather than solely relying on material selection, the manufacturing process remains relatively simple while achieving low via resistance
Solution Approach 2:
The method changes via geometric parameters including diameter, taper angle (60°-120°), and cross-sectional area to reduce via resistance. By controlling these physical parameters during via formation, the patent achieves lower resistance without requiring complex multi-material approaches, maintaining manufacturing simplicity while improving electrical performance
Data Source
AI summary
Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.